media: ti-vpe: cal: improve enable_irqs
authorTomi Valkeinen <tomi.valkeinen@ti.com>
Wed, 25 Mar 2020 12:14:53 +0000 (13:14 +0100)
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Tue, 14 Apr 2020 10:46:01 +0000 (12:46 +0200)
IRQENABLE_SET registers are (usually) not meant to be read, only written
to. The current driver needlessly uses read-modify-write cycle to enable
IRQ bits.

The read-modify-write has no bad side effects here, but it's still
better to clean this up by only using write.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
drivers/media/platform/ti-vpe/cal.c

index 9dd6de14189b8db1455d145834d70d9b07d079e8..76d55c76d938bb6f738d1bfdce1f479d6cd8b186 100644 (file)
@@ -706,16 +706,16 @@ static void cal_quickdump_regs(struct cal_dev *dev)
  */
 static void enable_irqs(struct cal_ctx *ctx)
 {
+       u32 val;
+
        /* Enable IRQ_WDMA_END 0/1 */
-       reg_write_field(ctx->dev,
-                       CAL_HL_IRQENABLE_SET(2),
-                       CAL_HL_IRQ_ENABLE,
-                       CAL_HL_IRQ_MASK(ctx->csi2_port));
+       val = 0;
+       set_field(&val, CAL_HL_IRQ_ENABLE, CAL_HL_IRQ_MASK(ctx->csi2_port));
+       reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(2), val);
        /* Enable IRQ_WDMA_START 0/1 */
-       reg_write_field(ctx->dev,
-                       CAL_HL_IRQENABLE_SET(3),
-                       CAL_HL_IRQ_ENABLE,
-                       CAL_HL_IRQ_MASK(ctx->csi2_port));
+       val = 0;
+       set_field(&val, CAL_HL_IRQ_ENABLE, CAL_HL_IRQ_MASK(ctx->csi2_port));
+       reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(3), val);
        /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
        reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0xFF000000);
 }