cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute

Export the QoS Throttling Group ID from the CXL Fixed Memory Window
Structure (CFMWS) under the root decoder sysfs attributes as qos_class.

CXL rev3.0 9.17.1.3 CXL Fixed Memory Window Structure (CFMWS)

cxl cli will use this id to match with the _DSM retrieved id for a
hot-plugged CXL memory device DPA memory range to make sure that the
DPA range is under the right CFMWS window.

Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/169713681699.2205276.14475306324720093079.stgit@djiang5-mobl3
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
index 087f762ebfd534e171434833fda4d772bd04ec1f..44ffbbb36654800a3705b8e6deef3a38af6c4027 100644 (file)
--- a/Documentation/ABI/testing/sysfs-bus-cxl
+++ b/Documentation/ABI/testing/sysfs-bus-cxl
@@ -369,6 +369,21 @@ Description:
                provided it is currently idle / not bound to a driver.
 
 
+What:          /sys/bus/cxl/devices/decoderX.Y/qos_class
+Date:          May, 2023
+KernelVersion: v6.5
+Contact:       linux-cxl@vger.kernel.org
+Description:
+               (RO) For CXL host platforms that support "QoS Telemmetry" this
+               root-decoder-only attribute conveys a platform specific cookie
+               that identifies a QoS performance class for the CXL Window.
+               This class-id can be compared against a similar "qos_class"
+               published for each memory-type that an endpoint supports. While
+               it is not required that endpoints map their local memory-class
+               to a matching platform class, mismatches are not recommended and
+               there are platform specific side-effects that may result.
+
+
 What:          /sys/bus/cxl/devices/regionZ/uuid
 Date:          May, 2022
 KernelVersion: v6.0

diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index 40d055560e52fd2298fa3400384b686e37413b32..2034eb4ce83fb7531be4148e4db0679a39b4587b 100644 (file)
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -289,6 +289,9 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
                        }
                }
        }
+
+       cxlrd->qos_class = cfmws->qtg_id;
+
        rc = cxl_decoder_add(cxld, target_map);
 err_xormap:
        if (rc)

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 7ca01a834e188c8f09f2676b8c79689279acbabe..fc31ff8954c00c8076f51177827b8a997e17a521 100644 (file)
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -278,6 +278,15 @@ static ssize_t interleave_ways_show(struct device *dev,
 
 static DEVICE_ATTR_RO(interleave_ways);
 
+static ssize_t qos_class_show(struct device *dev,
+                             struct device_attribute *attr, char *buf)
+{
+       struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
+
+       return sysfs_emit(buf, "%d\n", cxlrd->qos_class);
+}
+static DEVICE_ATTR_RO(qos_class);
+
 static struct attribute *cxl_decoder_base_attrs[] = {
        &dev_attr_start.attr,
        &dev_attr_size.attr,
@@ -297,6 +306,7 @@ static struct attribute *cxl_decoder_root_attrs[] = {
        &dev_attr_cap_type2.attr,
        &dev_attr_cap_type3.attr,
        &dev_attr_target_list.attr,
+       &dev_attr_qos_class.attr,
        SET_CXL_REGION_ATTR(create_pmem_region)
        SET_CXL_REGION_ATTR(create_ram_region)
        SET_CXL_REGION_ATTR(delete_region)
@@ -1691,6 +1701,7 @@ struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
        }
 
        atomic_set(&cxlrd->region_id, rc);
+       cxlrd->qos_class = CXL_QOS_CLASS_INVALID;
        return cxlrd;
 }
 EXPORT_SYMBOL_NS_GPL(cxl_root_decoder_alloc, CXL);

diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 76d92561af29499d2fe14629bdd11247039d5dab..eb7924648cb083a5121aba6b671cfc7940abcaad 100644 (file)
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -321,6 +321,7 @@ enum cxl_decoder_type {
  */
 #define CXL_DECODER_MAX_INTERLEAVE 16
 
+#define CXL_QOS_CLASS_INVALID -1
 
 /**
  * struct cxl_decoder - Common CXL HDM Decoder Attributes
@@ -432,6 +433,7 @@ typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd,
  * @calc_hb: which host bridge covers the n'th position by granularity
  * @platform_data: platform specific configuration data
  * @range_lock: sync region autodiscovery by address range
+ * @qos_class: QoS performance class cookie
  * @cxlsd: base cxl switch decoder
  */
 struct cxl_root_decoder {
@@ -440,6 +442,7 @@ struct cxl_root_decoder {
        cxl_calc_hb_fn calc_hb;
        void *platform_data;
        struct mutex range_lock;
+       int qos_class;
        struct cxl_switch_decoder cxlsd;
 };