clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk down

The gcc_mss_q6_bimc_axi_clk clock depends on the bimc_ddr_clk_src clock.
Move it down in the file to come after the source clock.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220704172453.838303-6-dmitry.baryshkov@linaro.org

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 1a6f5eb09d06806e27741d7953334cd2a4f97b90..f965cde0e8d558292a34038abe4c5d948bf2e718 100644 (file)
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -2629,23 +2629,6 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
        },
 };
 
-static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
-       .halt_reg = 0x49004,
-       .clkr = {
-               .enable_reg = 0x49004,
-               .enable_mask = BIT(0),
-               .hw.init = &(struct clk_init_data){
-                       .name = "gcc_mss_q6_bimc_axi_clk",
-                       .parent_names = (const char *[]){
-                               "bimc_ddr_clk_src",
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
 static struct clk_branch gcc_oxili_ahb_clk = {
        .halt_reg = 0x59028,
        .clkr = {
@@ -2812,6 +2795,23 @@ static struct clk_rcg2 bimc_ddr_clk_src = {
        },
 };
 
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
+       .halt_reg = 0x49004,
+       .clkr = {
+               .enable_reg = 0x49004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_mss_q6_bimc_axi_clk",
+                       .parent_names = (const char *[]){
+                               "bimc_ddr_clk_src",
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gcc_apss_tcu_clk = {
        .halt_reg = 0x12018,
        .clkr = {