drm/amd/display: Check pipe offset before setting vblank

pipe_ctx has a size of MAX_PIPES so checking its index before accessing
the array.

This fixes an OVERRUN issue reported by Coverity.

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index 1c0d89e675da5e1f41e42522d14cdf785ed66494..bb576a9c5fdbd52f7c3451704f929e905c5eca34 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -211,8 +211,12 @@ bool dce110_vblank_set(struct irq_service *irq_service,
                                                   info->ext_id);
        uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
 
-       struct timing_generator *tg =
-                       dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
+       struct timing_generator *tg;
+
+       if (pipe_offset >= MAX_PIPES)
+               return false;
+
+       tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
 
        if (enable) {
                if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {