bool                            in_suspend;
        bool                            in_hibernate;
 
-       bool                            in_gpu_reset;
+       atomic_t                        in_gpu_reset;
        enum pp_mp1_state               mp1_state;
        struct mutex  lock_reset;
        struct amdgpu_doorbell_index doorbell_index;
        return adev->gmc.tmz_enabled;
 }
 
+static inline int amdgpu_in_reset(struct amdgpu_device *adev)
+{
+       return atomic_read(&adev->in_gpu_reset);
+}
 #endif
 
        uint32_t temp;
        struct v10_compute_mqd *m = get_mqd(mqd);
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EIO;
 
 #if 0
 
        unsigned long flags, end_jiffies;
        int retry;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EIO;
 
        acquire_queue(kgd, pipe_id, queue_id);
 
        int retry;
        struct vi_mqd *m = get_mqd(mqd);
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EIO;
 
        acquire_queue(kgd, pipe_id, queue_id);
 
        uint32_t temp;
        struct v9_mqd *m = get_mqd(mqd);
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EIO;
 
        acquire_queue(kgd, pipe_id, queue_id);
 
 
        poll_wait(file, &adev->autodump.gpu_hang, poll_table);
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return POLLIN | POLLRDNORM | POLLWRNORM;
 
        return 0;
 
                        if (adev->ip_blocks[i].status.hw == true)
                                break;
 
-                       if (adev->in_gpu_reset || adev->in_suspend) {
+                       if (amdgpu_in_reset(adev) || adev->in_suspend) {
                                r = adev->ip_blocks[i].version->funcs->resume(adev);
                                if (r) {
                                        DRM_ERROR("resume of IP block <%s> failed %d\n",
                        AMDGPU_RESET_MAGIC_NUM))
                return true;
 
-       if (!adev->in_gpu_reset)
+       if (!amdgpu_in_reset(adev))
                return false;
 
        /*
        mutex_init(&adev->mn_lock);
        mutex_init(&adev->virt.vf_errors.lock);
        hash_init(adev->mn_hash);
+       atomic_set(&adev->in_gpu_reset, 0);
        mutex_init(&adev->lock_reset);
        mutex_init(&adev->psp.mutex);
        mutex_init(&adev->notifier_lock);
        return r;
 }
 
-static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
+static bool amdgpu_device_lock_adev(struct amdgpu_device *adev)
 {
-       if (trylock) {
-               if (!mutex_trylock(&adev->lock_reset))
-                       return false;
-       } else
-               mutex_lock(&adev->lock_reset);
+       if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0)
+               return false;
+
+       mutex_lock(&adev->lock_reset);
 
        atomic_inc(&adev->gpu_reset_counter);
-       adev->in_gpu_reset = true;
        switch (amdgpu_asic_reset_method(adev)) {
        case AMD_RESET_METHOD_MODE1:
                adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
 {
        amdgpu_vf_error_trans_all(adev);
        adev->mp1_state = PP_MP1_STATE_NONE;
-       adev->in_gpu_reset = false;
+       atomic_set(&adev->in_gpu_reset, 0);
        mutex_unlock(&adev->lock_reset);
 }
 
         * We always reset all schedulers for device and all devices for XGMI
         * hive so that should take care of them too.
         */
-       hive = amdgpu_get_xgmi_hive(adev, true);
-       if (hive && !mutex_trylock(&hive->reset_lock)) {
-               DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
-                         job ? job->base.id : -1, hive->hive_id);
-               mutex_unlock(&hive->hive_lock);
-               return 0;
+       hive = amdgpu_get_xgmi_hive(adev, false);
+       if (hive) {
+               if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) {
+                       DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
+                               job ? job->base.id : -1, hive->hive_id);
+                       return 0;
+               }
+               mutex_lock(&hive->hive_lock);
        }
 
        /*
 
        /* block all schedulers and reset given job's ring */
        list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
-               if (!amdgpu_device_lock_adev(tmp_adev, !hive)) {
+               if (!amdgpu_device_lock_adev(tmp_adev)) {
                        DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
                                  job ? job->base.id : -1);
                        mutex_unlock(&hive->hive_lock);
        }
 
        if (hive) {
-               mutex_unlock(&hive->reset_lock);
+               atomic_set(&hive->in_reset, 0);
                mutex_unlock(&hive->hive_lock);
        }
 
 
         *
         * also don't wait anymore for IRQ context
         * */
-       if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+       if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
                goto failed_kiq_read;
 
        might_sleep();
         *
         * also don't wait anymore for IRQ context
         * */
-       if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+       if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
                goto failed_kiq_write;
 
        might_sleep();
 
                return 0;
 
 
-       if (adev->in_gpu_reset && ras && ras->supported) {
+       if (amdgpu_in_reset(adev) && ras && ras->supported) {
                ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
                if (ret) {
                        DRM_WARN("Failed to set MP1 state prepare for reload\n");
        int ret;
        struct psp_context *psp = &adev->psp;
 
-       if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
+       if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
                psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
                goto skip_memalloc;
        }
 
                        amdgpu_ras_request_reset_on_boot(adev,
                                        ras_block->block);
                        return 0;
-               } else if (adev->in_suspend || adev->in_gpu_reset) {
+               } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
                        /* in resume phase, if fail to enable ras,
                         * clean up all ras fs nodes, and disable ras */
                        goto cleanup;
        }
 
        /* in resume phase, no need to create ras fs node */
-       if (adev->in_suspend || adev->in_gpu_reset)
+       if (adev->in_suspend || amdgpu_in_reset(adev))
                return 0;
 
        if (ih_info->cb) {
 
        uint64_t size;
        int r;
 
-       if (!adev->mman.initialized || adev->in_gpu_reset ||
+       if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
            adev->mman.buffer_funcs_enabled == enable)
                return;
 
 
        struct amdgpu_firmware_info *ucode = NULL;
 
  /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
-       if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
+       if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
                return 0;
        /*
         * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
 
 #define amdgpu_sriov_is_pp_one_vf(adev) \
        ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
 #define amdgpu_sriov_is_debug(adev) \
-       ((!adev->in_gpu_reset) && adev->virt.tdr_debug)
+       ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
 #define amdgpu_sriov_is_normal(adev) \
-       ((!adev->in_gpu_reset) && (!adev->virt.tdr_debug))
+       ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
 
 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
 
        tmp->hive_id = adev->gmc.xgmi.hive_id;
        INIT_LIST_HEAD(&tmp->device_list);
        mutex_init(&tmp->hive_lock);
-       mutex_init(&tmp->reset_lock);
+       atomic_set(&tmp->in_reset, 0);
        task_barrier_init(&tmp->tb);
 
        if (lock)
        if(!(--hive->number_devices)){
                amdgpu_xgmi_sysfs_destroy(adev, hive);
                mutex_destroy(&hive->hive_lock);
-               mutex_destroy(&hive->reset_lock);
        }
 
        return psp_xgmi_terminate(&adev->psp);
 
        uint64_t                hive_id;
        struct list_head        device_list;
        int number_devices;
-       struct mutex hive_lock, reset_lock;
+       struct mutex hive_lock;
        struct kobject *kobj;
        struct device_attribute dev_attr;
        struct amdgpu_device *adev;
+       atomic_t in_reset;
        int hi_req_count;
        struct amdgpu_device *hi_req_gpu;
        struct task_barrier tb;
 
        struct v10_gfx_mqd *mqd = ring->mqd_ptr;
        int mqd_idx = ring - &adev->gfx.gfx_ring[0];
 
-       if (!adev->in_gpu_reset && !adev->in_suspend) {
+       if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
                memset((void *)mqd, 0, sizeof(*mqd));
                mutex_lock(&adev->srbm_mutex);
                nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
                mutex_unlock(&adev->srbm_mutex);
                if (adev->gfx.me.mqd_backup[mqd_idx])
                        memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
-       } else if (adev->in_gpu_reset) {
+       } else if (amdgpu_in_reset(adev)) {
                /* reset mqd with the backup copy */
                if (adev->gfx.me.mqd_backup[mqd_idx])
                        memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
 
        gfx_v10_0_kiq_setting(ring);
 
-       if (adev->in_gpu_reset) { /* for GPU_RESET case */
+       if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
                /* reset MQD to a clean status */
                if (adev->gfx.mec.mqd_backup[mqd_idx])
                        memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
        struct v10_compute_mqd *mqd = ring->mqd_ptr;
        int mqd_idx = ring - &adev->gfx.compute_ring[0];
 
-       if (!adev->in_gpu_reset && !adev->in_suspend) {
+       if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
                memset((void *)mqd, 0, sizeof(*mqd));
                mutex_lock(&adev->srbm_mutex);
                nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
 
                if (adev->gfx.mec.mqd_backup[mqd_idx])
                        memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
-       } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
+       } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
                /* reset MQD to a clean status */
                if (adev->gfx.mec.mqd_backup[mqd_idx])
                        memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
 
 
        gfx_v8_0_kiq_setting(ring);
 
-       if (adev->in_gpu_reset) { /* for GPU_RESET case */
+       if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
                /* reset MQD to a clean status */
                if (adev->gfx.mec.mqd_backup[mqd_idx])
                        memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
        struct vi_mqd *mqd = ring->mqd_ptr;
        int mqd_idx = ring - &adev->gfx.compute_ring[0];
 
-       if (!adev->in_gpu_reset && !adev->in_suspend) {
+       if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
                memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
                ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
                ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
 
                if (adev->gfx.mec.mqd_backup[mqd_idx])
                        memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
-       } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
+       } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
                /* reset MQD to a clean status */
                if (adev->gfx.mec.mqd_backup[mqd_idx])
                        memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
 
 
        gfx_v9_0_kiq_setting(ring);
 
-       if (adev->in_gpu_reset) { /* for GPU_RESET case */
+       if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
                /* reset MQD to a clean status */
                if (adev->gfx.mec.mqd_backup[mqd_idx])
                        memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
        struct v9_mqd *mqd = ring->mqd_ptr;
        int mqd_idx = ring - &adev->gfx.compute_ring[0];
 
-       if (!adev->in_gpu_reset && !adev->in_suspend) {
+       if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
                memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
                ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
                ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
 
                if (adev->gfx.mec.mqd_backup[mqd_idx])
                        memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
-       } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
+       } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
                /* reset MQD to a clean status */
                if (adev->gfx.mec.mqd_backup[mqd_idx])
                        memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
        /* Use deinitialize sequence from CAIL when unbinding device from driver,
         * otherwise KIQ is hanging when binding back
         */
-       if (!adev->in_gpu_reset && !adev->in_suspend) {
+       if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
                mutex_lock(&adev->srbm_mutex);
                soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
                                adev->gfx.kiq.ring.pipe,
         *
         * also don't wait anymore for IRQ context
         * */
-       if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+       if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
                goto failed_kiq_read;
 
        might_sleep();
 
         */
        if (adev->gfx.kiq.ring.sched.ready &&
            (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
-           !adev->in_gpu_reset) {
+           !amdgpu_in_reset(adev)) {
 
                struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
                const unsigned eng = 17;
 
        if (!adev->mman.buffer_funcs_enabled ||
            !adev->ib_pool_ready ||
-           adev->in_gpu_reset ||
+           amdgpu_in_reset(adev) ||
            ring->sched.ready == false) {
                gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
                mutex_unlock(&adev->mman.gtt_window_lock);
 
        int vmid;
        unsigned int tmp;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EIO;
 
        for (vmid = 1; vmid < 16; vmid++) {
 
        int vmid;
        unsigned int tmp;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EIO;
 
        for (vmid = 1; vmid < 16; vmid++) {
 
         */
        if (adev->gfx.kiq.ring.sched.ready &&
                        (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
-                       !adev->in_gpu_reset) {
+                       !amdgpu_in_reset(adev)) {
                uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
                uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 
        struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
        struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EIO;
 
        if (ring->sched.ready) {
 
         */
        locked = mutex_trylock(&adev->lock_reset);
        if (locked)
-               adev->in_gpu_reset = true;
+               atomic_set(&adev->in_gpu_reset, 1);
 
        do {
                if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)
 
 flr_done:
        if (locked) {
-               adev->in_gpu_reset = false;
+               atomic_set(&adev->in_gpu_reset, 0);
                mutex_unlock(&adev->lock_reset);
        }
 
 
         */
        locked = mutex_trylock(&adev->lock_reset);
        if (locked)
-               adev->in_gpu_reset = true;
+               atomic_set(&adev->in_gpu_reset, 1);
 
        do {
                if (xgpu_nv_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)
 
 flr_done:
        if (locked) {
-               adev->in_gpu_reset = false;
+               atomic_set(&adev->in_gpu_reset, 0);
                mutex_unlock(&adev->lock_reset);
        }
 
 
        struct amdgpu_display_manager *dm = &adev->dm;
        int ret = 0;
 
-       if (adev->in_gpu_reset) {
+       if (amdgpu_in_reset(adev)) {
                mutex_lock(&dm->dc_lock);
                dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
 
        struct dc_state *dc_state;
        int i, r, j;
 
-       if (adev->in_gpu_reset) {
+       if (amdgpu_in_reset(adev)) {
                dc_state = dm->cached_dc_state;
 
                r = dm_dmub_hw_init(adev);
 
        enum amd_pm_state_type pm;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        enum amd_pm_state_type  state;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        if (strncmp("battery", buf, strlen("battery")) == 0)
        enum amd_dpm_forced_level level = 0xff;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        enum amd_dpm_forced_level current_level = 0xff;
        int ret = 0;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        if (strncmp("low", buf, strlen("low")) == 0) {
        struct pp_states_info data;
        int i, buf_len, ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        enum amd_pm_state_type pm = 0;
        int i = 0, ret = 0;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        struct drm_device *ddev = dev_get_drvdata(dev);
        struct amdgpu_device *adev = ddev->dev_private;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        if (adev->pp_force_state_enabled)
        unsigned long idx;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        if (strlen(buf) == 1)
        char *table = NULL;
        int size, ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        struct amdgpu_device *adev = ddev->dev_private;
        int ret = 0;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        const char delimiter[3] = {' ', '\n', '\0'};
        uint32_t type;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        if (count > 127)
        ssize_t size;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        uint64_t featuremask;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = kstrtou64(buf, 0, &featuremask);
        ssize_t size;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        ssize_t size;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        int ret;
        uint32_t mask = 0;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = amdgpu_read_mask(buf, count, &mask);
        ssize_t size;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        uint32_t mask = 0;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = amdgpu_read_mask(buf, count, &mask);
        ssize_t size;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        int ret;
        uint32_t mask = 0;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = amdgpu_read_mask(buf, count, &mask);
        ssize_t size;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        int ret;
        uint32_t mask = 0;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = amdgpu_read_mask(buf, count, &mask);
        ssize_t size;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        int ret;
        uint32_t mask = 0;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = amdgpu_read_mask(buf, count, &mask);
        ssize_t size;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        int ret;
        uint32_t mask = 0;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = amdgpu_read_mask(buf, count, &mask);
        uint32_t value = 0;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        int ret;
        long int value;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = kstrtol(buf, 0, &value);
        uint32_t value = 0;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        int ret;
        long int value;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = kstrtol(buf, 0, &value);
        ssize_t size;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        long int profile_mode = 0;
        const char delimiter[3] = {' ', '\n', '\0'};
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        tmp[0] = *(buf);
        struct amdgpu_device *adev = ddev->dev_private;
        int r, value, size = sizeof(value);
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        r = pm_runtime_get_sync(ddev->dev);
        struct amdgpu_device *adev = ddev->dev_private;
        int r, value, size = sizeof(value);
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        r = pm_runtime_get_sync(ddev->dev);
        uint64_t count0 = 0, count1 = 0;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        if (adev->flags & AMD_IS_APU)
        struct drm_device *ddev = dev_get_drvdata(dev);
        struct amdgpu_device *adev = ddev->dev_private;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        if (adev->unique_id)
        ssize_t size = 0;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(ddev->dev);
        int channel = to_sensor_dev_attr(attr)->index;
        int r, temp = 0, size = sizeof(temp);
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        if (channel >= PP_TEMP_MAX)
        u32 pwm_mode = 0;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(adev->ddev->dev);
        int err, ret;
        int value;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        err = kstrtoint(buf, 10, &value);
        u32 value;
        u32 pwm_mode;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        err = pm_runtime_get_sync(adev->ddev->dev);
        int err;
        u32 speed = 0;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        err = pm_runtime_get_sync(adev->ddev->dev);
        int err;
        u32 speed = 0;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        err = pm_runtime_get_sync(adev->ddev->dev);
        u32 size = sizeof(min_rpm);
        int r;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        r = pm_runtime_get_sync(adev->ddev->dev);
        u32 size = sizeof(max_rpm);
        int r;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        r = pm_runtime_get_sync(adev->ddev->dev);
        int err;
        u32 rpm = 0;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        err = pm_runtime_get_sync(adev->ddev->dev);
        u32 value;
        u32 pwm_mode;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        err = pm_runtime_get_sync(adev->ddev->dev);
        u32 pwm_mode = 0;
        int ret;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        ret = pm_runtime_get_sync(adev->ddev->dev);
        int value;
        u32 pwm_mode;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        err = kstrtoint(buf, 10, &value);
        u32 vddgfx;
        int r, size = sizeof(vddgfx);
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        r = pm_runtime_get_sync(adev->ddev->dev);
        u32 vddnb;
        int r, size = sizeof(vddnb);
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        /* only APUs have vddnb */
        int r, size = sizeof(u32);
        unsigned uw;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        r = pm_runtime_get_sync(adev->ddev->dev);
        ssize_t size;
        int r;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        r = pm_runtime_get_sync(adev->ddev->dev);
        ssize_t size;
        int r;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        r = pm_runtime_get_sync(adev->ddev->dev);
        int err;
        u32 value;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        if (amdgpu_sriov_vf(adev))
        uint32_t sclk;
        int r, size = sizeof(sclk);
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        r = pm_runtime_get_sync(adev->ddev->dev);
        uint32_t mclk;
        int r, size = sizeof(mclk);
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        r = pm_runtime_get_sync(adev->ddev->dev);
        u32 flags = 0;
        int r;
 
-       if (adev->in_gpu_reset)
+       if (amdgpu_in_reset(adev))
                return -EPERM;
 
        r = pm_runtime_get_sync(dev->dev);
 
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
        int ret = 0;
-       bool use_baco = (adev->in_gpu_reset &&
+       bool use_baco = (amdgpu_in_reset(adev) &&
                         (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
                (adev->in_runpm && amdgpu_asic_supports_baco(adev));
 
 
        struct amdgpu_device *adev = smu->adev;
        int ret = 0;
        bool use_baco = !smu->is_apu &&
-               ((adev->in_gpu_reset &&
+               ((amdgpu_in_reset(adev) &&
                  (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
                 ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));