arm64: dts: zynqmp: Add mode-pin GPIO controller DT node

Add mode-pin GPIO controller DT node in zynqmp.dtsi and wire it to usb0
controller. All Xilinx evaluation boards are using modepin gpio for ULPI
reset that's why wire it directly in zynqmp instead of c&p the same line to
every board specific file.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/69924a8e2c01e5a1d25d098adc53224ddb841f46.1670594085.git.michal.simek@amd.com

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 130df216fa1bbf9f82018c4f8548ee6dbf513d29..9793a4e652d947379d30241631049ac2a0ea7101 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -13,6 +13,7 @@
  */
 
 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/power/xlnx-zynqmp-power.h>
 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
 
@@ -199,6 +200,12 @@
                                compatible = "xlnx,zynqmp-pinctrl";
                                status = "disabled";
                        };
+
+                       modepin_gpio: gpio {
+                               compatible = "xlnx,zynqmp-gpio-modepin";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                       };
                };
        };
 
@@ -847,6 +854,7 @@
                                 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
                                 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
                        reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
+                       reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
                        ranges;
 
                        dwc3_0: usb@fe200000 {