drm/i915/dp_mst: Program the DSC PPS SDP for each stream
authorImre Deak <imre.deak@intel.com>
Tue, 24 Oct 2023 01:09:10 +0000 (04:09 +0300)
committerImre Deak <imre.deak@intel.com>
Wed, 8 Nov 2023 15:22:14 +0000 (17:22 +0200)
Atm the DSC PPS SDP is programmed only if the first stream is compressed
and then it's programmed only for the first stream. This left all other
compressed streams blank. Program the SDP for all streams.

v2:
- Rebase on upstream include "intel_vdsc.h" change.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231107001505.3370108-3-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_ddi.c
drivers/gpu/drm/i915/display/intel_dp_mst.c

index c75fd00e360ac51325ab568b590889792f375c61..87fa7f73692541c5c9ef4dc456eb4ffaedb9e012 100644 (file)
@@ -2505,7 +2505,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
        /* 6.o Configure and enable FEC if needed */
        intel_ddi_enable_fec(encoder, crtc_state);
 
-       intel_dsc_dp_pps_write(encoder, crtc_state);
+       if (!is_mst)
+               intel_dsc_dp_pps_write(encoder, crtc_state);
 }
 
 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2643,7 +2644,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
        /* 7.l Configure and enable FEC if needed */
        intel_ddi_enable_fec(encoder, crtc_state);
 
-       intel_dsc_dp_pps_write(encoder, crtc_state);
+       if (!is_mst)
+               intel_dsc_dp_pps_write(encoder, crtc_state);
 }
 
 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2705,10 +2707,10 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 
        intel_ddi_enable_fec(encoder, crtc_state);
 
-       if (!is_mst)
+       if (!is_mst) {
                intel_ddi_enable_transcoder_clock(encoder, crtc_state);
-
-       intel_dsc_dp_pps_write(encoder, crtc_state);
+               intel_dsc_dp_pps_write(encoder, crtc_state);
+       }
 }
 
 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
index c9faac174aa2c0629cd1ef09fc545f7d662a27d0..5efc3cea73e5253f09eb5b9c951e80a0d3931abb 100644 (file)
@@ -860,6 +860,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
        if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
                intel_ddi_enable_transcoder_clock(encoder, pipe_config);
 
+       intel_dsc_dp_pps_write(&dig_port->base, pipe_config);
        intel_ddi_set_dp_msa(pipe_config, conn_state);
 }