arm64: dts: qcom: x1e80100: Add SPMI support

The X1E80100 platform implements the v7 SPMI arbiter, which means it
implements two separate buses. The difference, when compared to existing
platforms that also implement v7 SPMI arbiter, is that this is the first
platform that actually has boards with secondary bus populated with some
PMICs. This is why it needs to have 2 separate buses as child nodes of
the arbiter.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240222-x1e80100-dts-smb2360-v3-1-85a691d4f68a@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 26d779ade489e46930fe758084d8ed843a3e38a2..fa04a24173a740c732842feb5a718136f0ee341e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -4221,6 +4221,48 @@
                        #clock-cells = <0>;
                };
 
+               spmi: arbiter@c400000 {
+                       compatible = "qcom,x1e80100-spmi-pmic-arb";
+                       reg = <0 0x0c400000 0 0x3000>,
+                             <0 0x0c500000 0 0x400000>,
+                             <0 0x0c440000 0 0x80000>;
+                       reg-names = "core", "chnls", "obsrvr";
+
+                       qcom,ee = <0>;
+                       qcom,channel = <0>;
+
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       spmi_bus0: spmi@c42d000 {
+                               reg = <0 0x0c42d000 0 0x4000>,
+                                     <0 0x0c4c0000 0 0x10000>;
+                               reg-names = "cnfg", "intr";
+
+                               interrupt-names = "periph_irq";
+                               interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-controller;
+                               #interrupt-cells = <4>;
+
+                               #address-cells = <2>;
+                               #size-cells = <0>;
+                       };
+
+                       spmi_bus1: spmi@c432000 {
+                               reg = <0 0x0c432000 0 0x4000>,
+                                     <0 0x0c4d0000 0 0x10000>;
+                               reg-names = "cnfg", "intr";
+
+                               interrupt-names = "periph_irq";
+                               interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-controller;
+                               #interrupt-cells = <4>;
+
+                               #address-cells = <2>;
+                               #size-cells = <0>;
+                       };
+               };
 
                tlmm: pinctrl@f100000 {
                        compatible = "qcom,x1e80100-tlmm";