riscv/cmpxchg: Implement cmpxchg for variables of size 1 and 2

cmpxchg for variables of size 1-byte and 2-bytes is not yet available for
riscv, even though its present in other architectures such as arm64 and
x86. This could lead to not being able to implement some locking mechanisms
or requiring some rework to make it work properly.

Implement 1-byte and 2-bytes cmpxchg in order to achieve parity with other
architectures.

Signed-off-by: Leonardo Bras <leobras@redhat.com>
Tested-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20240103163203.72768-6-leobras@redhat.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index e3e0ac7ba061bc18749fd103877ae8b8f39f1e3d..ac9d0eeb74e67599ed7d7b78a9dc13d4c007eb3f 100644 (file)
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -72,6 +72,35 @@
  * indicated by comparing RETURN with OLD.
  */
 
+#define __arch_cmpxchg_masked(sc_sfx, prepend, append, r, p, o, n)     \
+({                                                                     \
+       u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3);                     \
+       ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE;  \
+       ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0)   \
+                       << __s;                                         \
+       ulong __newx = (ulong)(n) << __s;                               \
+       ulong __oldx = (ulong)(o) << __s;                               \
+       ulong __retx;                                                   \
+       ulong __rc;                                                     \
+                                                                       \
+       __asm__ __volatile__ (                                          \
+               prepend                                                 \
+               "0:     lr.w %0, %2\n"                                  \
+               "       and  %1, %0, %z5\n"                             \
+               "       bne  %1, %z3, 1f\n"                             \
+               "       and  %1, %0, %z6\n"                             \
+               "       or   %1, %1, %z4\n"                             \
+               "       sc.w" sc_sfx " %1, %1, %2\n"                    \
+               "       bnez %1, 0b\n"                                  \
+               append                                                  \
+               "1:\n"                                                  \
+               : "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b))      \
+               : "rJ" ((long)__oldx), "rJ" (__newx),                   \
+                 "rJ" (__mask), "rJ" (~__mask)                         \
+               : "memory");                                            \
+                                                                       \
+       r = (__typeof__(*(p)))((__retx & __mask) >> __s);               \
+})
 
 #define __arch_cmpxchg(lr_sfx, sc_sfx, prepend, append, r, p, co, o, n)        \
 ({                                                                     \
@@ -98,6 +127,11 @@
        __typeof__(*(__ptr)) __ret;                                     \
                                                                        \
        switch (sizeof(*__ptr)) {                                       \
+       case 1:                                                         \
+       case 2:                                                         \
+               __arch_cmpxchg_masked(sc_sfx, prepend, append,          \
+                                       __ret, __ptr, __old, __new);    \
+               break;                                                  \
        case 4:                                                         \
                __arch_cmpxchg(".w", ".w" sc_sfx, prepend, append,      \
                                __ret, __ptr, (long), __old, __new);    \