drm/amd/display: wake up ogam mem pwr before programming ocsc

[Description]
OGAM_MEM_PWR could stay in light up when driver woke up to update gamma.
either disable MEM_LOW power feature or set to OGAM_bypass could make artificial color distortion goes away.
Easy reproduce after LOW_MEM Power feature enables and resume from S3.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Julian Parkin <jparkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index 9bc5dd23d297e1f27ea0e00987da094e71b96c02..db311574f42fdc00c121781acbef606b5f3453a2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -72,6 +72,21 @@ void dpp20_read_state(struct dpp *dpp_base,
        }
 }
 
+void dpp2_power_on_obuf(
+               struct dpp *dpp_base,
+       bool power_on)
+{
+       struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
+
+       REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);
+
+       REG_UPDATE(OBUF_MEM_PWR_CTRL,
+                       OBUF_MEM_PWR_FORCE, power_on == true ? 0:1);
+
+       REG_UPDATE(DSCL_MEM_PWR_CTRL,
+                       LUT_MEM_PWR_FORCE, power_on == true ? 0:1);
+}
+
 void dpp2_dummy_program_input_lut(
                struct dpp *dpp_base,
                const struct dc_gamma *gamma)
@@ -227,6 +242,7 @@ static void dpp2_cnv_setup (
                                CUR0_ENABLE, 0);
 
        }
+       dpp2_power_on_obuf(dpp_base, true);
 
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
index 59b67ed57c19396e91ead4dc71b51f43c881aefd..1f5d99a6d240195a9f7aa2af8155fb0588efeab1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
@@ -162,7 +162,9 @@
        SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \
        SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \
        SRI(CM_SHAPER_LUT_DATA, CM, id), \
-       SRI(CURSOR_CONTROL, CURSOR0_, id)
+       SRI(CURSOR_CONTROL, CURSOR0_, id),\
+       SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
+       SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
 
 #define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\
        TF_REG_LIST_SH_MASK_DCN(mask_sh), \
@@ -554,7 +556,9 @@
        TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \
        TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \
        TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \
-       TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh)
+       TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\
+       TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
+       TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)
 
 #define TF_REG_FIELD_LIST_DCN2_0(type) \
        TF_REG_FIELD_LIST(type) \
@@ -585,7 +589,9 @@
        type COLOR_KEYER_BLUE_HIGH; \
        type CUR0_PIX_INV_MODE; \
        type CUR0_PIXEL_ALPHA_MOD_EN; \
-       type CUR0_ROM_EN
+       type CUR0_ROM_EN;\
+       type OBUF_MEM_PWR_FORCE;\
+       type LUT_MEM_PWR_FORCE
 
 struct dcn2_dpp_shift {
        TF_REG_FIELD_LIST_DCN2_0(uint8_t);
@@ -609,7 +615,9 @@ struct dcn2_dpp_mask {
        uint32_t COLOR_KEYER_ALPHA; \
        uint32_t COLOR_KEYER_RED; \
        uint32_t COLOR_KEYER_GREEN; \
-       uint32_t COLOR_KEYER_BLUE
+       uint32_t COLOR_KEYER_BLUE; \
+       uint32_t OBUF_MEM_PWR_CTRL;\
+       uint32_t DSCL_MEM_PWR_CTRL
 
 struct dcn2_dpp_registers {
        DPP_DCN2_REG_VARIABLE_LIST;
@@ -695,4 +703,7 @@ bool dpp2_construct(struct dcn20_dpp *dpp2,
        const struct dcn2_dpp_shift *tf_shift,
        const struct dcn2_dpp_mask *tf_mask);
 
+void dpp2_power_on_obuf(
+               struct dpp *dpp_base,
+       bool power_on);
 #endif /* __DC_HWSS_DCN20_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 5904d4d329df6d22a817dccea5a2703c7c89c0c7..4e9ac051d3d82a4c307c1358bb604d84a645178a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -631,6 +631,10 @@ void dcn20_program_output_csc(struct dc *dc,
 {
        struct mpc *mpc = dc->res_pool->mpc;
        enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
+       int mpcc_id = pipe_ctx->plane_res.hubp->inst;
+
+       if (mpc->funcs->power_on_mpc_mem_pwr)
+               mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 
        if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
                if (mpc->funcs->set_output_csc != NULL)
@@ -660,6 +664,8 @@ bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
         * if programming for all pipes is required then remove condition
         * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
         */
+       if (mpc->funcs->power_on_mpc_mem_pwr)
+               mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
        if ((pipe_ctx->top_pipe == NULL || dc_res_is_odm_head_pipe(pipe_ctx))
                        && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
                if (stream->out_transfer_func->type == TF_TYPE_HWPWL)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
index 17950d9e53cf9aab5012dad10ef86df0455a8df1..5a188b2bc033c92a340cdd2ae374f0a957d0e6d3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
@@ -233,14 +233,14 @@ static void mpc2_ogam_get_reg_field(
        reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
 }
 
-static void mpc20_power_on_ogam_lut(
+void mpc20_power_on_ogam_lut(
                struct mpc *mpc, int mpcc_id,
                bool power_on)
 {
        struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
 
        REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
-                       MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
+                       MPCC_OGAM_MEM_PWR_DIS, power_on == true ? 1:0);
 
 }
 
@@ -509,6 +509,7 @@ const struct mpc_funcs dcn20_mpc_funcs = {
        .set_output_csc = mpc2_set_output_csc,
        .set_ocsc_default = mpc2_set_ocsc_default,
        .set_output_gamma = mpc2_set_output_gamma,
+       .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
 };
 
 void dcn20_mpc_construct(struct dcn20_mpc *mpc20,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
index 9750095d2d73047510a9b0c249bb801fbd959848..9f53192da2dc399cce035e093344ad3311a34054 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
@@ -159,6 +159,7 @@
        SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\
        SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\
        SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
+       SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
        SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
        SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\
        SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\
@@ -173,6 +174,7 @@
        SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
        SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh)
 
+
 #define MPC_REG_FIELD_LIST_DCN2_0(type) \
        MPC_REG_FIELD_LIST(type)\
        type MPCC_BG_BPC;\
@@ -217,7 +219,8 @@
        type MPC_OUT_DENORM_CLAMP_MIN_G_Y;\
        type MPC_OUT_DENORM_CLAMP_MAX_B_CB;\
        type MPC_OUT_DENORM_CLAMP_MIN_B_CB;\
-       type MPCC_DISABLED;
+       type MPCC_DISABLED;\
+       type MPCC_OGAM_MEM_PWR_DIS;
 
 struct dcn20_mpc_registers {
        MPC_REG_VARIABLE_LIST_DCN2_0
@@ -282,4 +285,5 @@ void mpc2_set_output_gamma(
 
 void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);
 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
+void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index 9dde88d4571ce3af5145fe7c5bf43fd75a956ad7..58826be81395c9c1055eb21fa38d1958d1117eb9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -254,6 +254,10 @@ struct mpc_funcs {
                        struct mpc *mpc,
                        int mpcc_id,
                        const struct pwl_params *params);
+       void (*power_on_mpc_mem_pwr)(
+                       struct mpc *mpc,
+                       int mpcc_id,
+                       bool power_on);
 #endif
 
 };