PCI/DPC: Quirk PIO log size for certain Intel Root Ports

Some Root Ports on Intel Tiger Lake and Alder Lake systems support the RP
Extensions for DPC and the RP PIO Log registers but incorrectly advertise
an RP PIO Log Size of zero.  This means the kernel complains that:

  DPC: RP PIO log size 0 is invalid

and if DPC is triggered, the DPC driver will not dump the RP PIO Log
registers when it should.

This is caused by a BIOS bug and should be fixed the BIOS for future CPUs.

Add a quirk to set the correct RP PIO Log size for the affected Root Ports.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=209943
Link: https://lore.kernel.org/r/20220816102042.69125-1-mika.westerberg@linux.intel.com
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c
index 3e9afee02e8d1616bd4ab5278bc2e10e95f42a6b..f5ffea17c7f87207e1c413a430d94c3fce876942 100644 (file)
--- a/drivers/pci/pcie/dpc.c
+++ b/drivers/pci/pcie/dpc.c
@@ -335,11 +335,16 @@ void pci_dpc_init(struct pci_dev *pdev)
                return;
 
        pdev->dpc_rp_extensions = true;
-       pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
-       if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
-               pci_err(pdev, "RP PIO log size %u is invalid\n",
-                       pdev->dpc_rp_log_size);
-               pdev->dpc_rp_log_size = 0;
+
+       /* Quirks may set dpc_rp_log_size if device or firmware is buggy */
+       if (!pdev->dpc_rp_log_size) {
+               pdev->dpc_rp_log_size =
+                       (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
+               if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
+                       pci_err(pdev, "RP PIO log size %u is invalid\n",
+                               pdev->dpc_rp_log_size);
+                       pdev->dpc_rp_log_size = 0;
+               }
        }
 }
 

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 4944798e75b5a2fd58a31f6815046cd1bdd79a27..285acc4aaccc1e3f9cae1190ab09a19fb6eb5853 100644 (file)
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5956,3 +5956,39 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
 #endif
+
+#ifdef CONFIG_PCIE_DPC
+/*
+ * Intel Tiger Lake and Alder Lake BIOS has a bug that clears the DPC
+ * RP PIO Log Size of the integrated Thunderbolt PCIe Root Ports.
+ */
+static void dpc_log_size(struct pci_dev *dev)
+{
+       u16 dpc, val;
+
+       dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
+       if (!dpc)
+               return;
+
+       pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val);
+       if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
+               return;
+
+       if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {
+               pci_info(dev, "Overriding RP PIO Log Size to 4\n");
+               dev->dpc_rp_log_size = 4;
+       }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
+#endif