drm/msm/dpu: add division of drm_display_mode's hskew parameter

Setting up the timing engine when the physical encoder has a split role
neglects dividing the drm_display_mode's hskew parameter. Let's fix this
since this must also be done in preparation for implementing YUV420 over
DP.

Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579605/
Link: https://lore.kernel.org/r/20240222194025.25329-3-quic_parellan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 2aa72b57876457b4cdbfc8a8059f4425fd590444..c0bf388988cb95c5dbef7145f8aa294838f0f99b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -260,12 +260,14 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
                mode.htotal >>= 1;
                mode.hsync_start >>= 1;
                mode.hsync_end >>= 1;
+               mode.hskew >>= 1;
 
                DPU_DEBUG_VIDENC(phys_enc,
-                       "split_role %d, halve horizontal %d %d %d %d\n",
+                       "split_role %d, halve horizontal %d %d %d %d %d\n",
                        phys_enc->split_role,
                        mode.hdisplay, mode.htotal,
-                       mode.hsync_start, mode.hsync_end);
+                       mode.hsync_start, mode.hsync_end,
+                       mode.hskew);
        }
 
        drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);