drm/tegra: dp: Set channel coding on link configuration

Make use of ANSI 8B/10B channel coding if the DisplayPort sink supports
it.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c
index 757a0256592f30ec00cc8178ed9cba9e5712e3e2..ca287b50fad80a73a1a3046824f5dd8db17b36db 100644 (file)
--- a/drivers/gpu/drm/tegra/dp.c
+++ b/drivers/gpu/drm/tegra/dp.c
@@ -203,7 +203,7 @@ int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
  */
 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
 {
-       u8 values[2];
+       u8 values[2], value;
        int err;
 
        values[0] = drm_dp_link_rate_to_bw_code(link->rate);
@@ -216,5 +216,14 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
        if (err < 0)
                return err;
 
+       if (link->caps.channel_coding)
+               value = DP_SET_ANSI_8B10B;
+       else
+               value = 0;
+
+       err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, value);
+       if (err < 0)
+               return err;
+
        return 0;
 }