arm64: dts: qcom: qcs404: Enable CQE support for eMMC
authorVeerabhadrarao Badiganti <vbadigan@codeaurora.org>
Wed, 11 Mar 2020 17:14:21 +0000 (22:44 +0530)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Thu, 12 Mar 2020 05:43:43 +0000 (22:43 -0700)
Enabling CQE support for eMMC by supplying the correct reg name
and flag which indicates CQE support.

Also remove the redundant _mem suffix for reg names.

Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Link: https://lore.kernel.org/r/1583946863-24308-1-git-send-email-vbadigan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
arch/arm64/boot/dts/qcom/qcs404.dtsi

index 522d3ef72df5e50c017a41ddf22e4ee3e10975f7..afe69e8f3114c97e8d66da58fe5fd1a1012d3345 100644 (file)
 &sdcc1 {
        status = "ok";
 
+       supports-cqe;
        mmc-ddr-1_8v;
        mmc-hs400-1_8v;
        bus-width = <8>;
index 1eea064357790ce5285618da02756d3abcf8b1c2..f149a538c1cc61681263cd36d619e1c1ff7b7b61 100644 (file)
                sdcc1: sdcc@7804000 {
                        compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
                        reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
-                       reg-names = "hc_mem", "cmdq_mem";
+                       reg-names = "hc", "cqhci";
 
                        interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;