riscv: dts: microchip: convert isa detection to new properties

Convert the PolarFire SoC devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 104504352e99ce49ec4379b2b53ba1b6f2dc939c..a6faf24f1dbaf659eb9f0df6baadc34fa3246f52 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -22,6 +22,9 @@
                        i-cache-size = <16384>;
                        reg = <0>;
                        riscv,isa = "rv64imac";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
                        clocks = <&clkcfg CLK_CPU>;
                        status = "disabled";
 
@@ -48,6 +51,9 @@
                        mmu-type = "riscv,sv39";
                        reg = <1>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        clocks = <&clkcfg CLK_CPU>;
                        tlb-split;
                        next-level-cache = <&cctrllr>;
@@ -76,6 +82,9 @@
                        mmu-type = "riscv,sv39";
                        reg = <2>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        clocks = <&clkcfg CLK_CPU>;
                        tlb-split;
                        next-level-cache = <&cctrllr>;
@@ -104,6 +113,9 @@
                        mmu-type = "riscv,sv39";
                        reg = <3>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        clocks = <&clkcfg CLK_CPU>;
                        tlb-split;
                        next-level-cache = <&cctrllr>;
@@ -132,6 +144,9 @@
                        mmu-type = "riscv,sv39";
                        reg = <4>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        clocks = <&clkcfg CLK_CPU>;
                        tlb-split;
                        next-level-cache = <&cctrllr>;