u8 media_ver;
/** @supports_usm: Supports unified shared memory */
bool supports_usm;
+ /** @has_asid: Has address space ID */
+ bool has_asid;
/** @enable_guc: GuC submission enabled */
bool enable_guc;
/** @has_flat_ccs: Whether flat CCS metadata is used */
xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
xe_lrc_write_ctx_reg(lrc, CTX_RING_CTL,
RING_CTL_SIZE(lrc->ring.size) | RING_VALID);
- if (xe->info.supports_usm && vm) {
+ if (xe->info.has_asid && vm)
xe_lrc_write_ctx_reg(lrc, PVC_CTX_ASID,
(e->usm.acc_granularity <<
ACC_GRANULARITY_S) | vm->usm.asid);
+ if (xe->info.supports_usm && vm)
xe_lrc_write_ctx_reg(lrc, PVC_CTX_ACC_CTR_THOLD,
(e->usm.acc_notify << ACC_NOTIFY_S) |
e->usm.acc_trigger);
- }
lrc->desc = GEN8_CTX_VALID;
lrc->desc |= INTEL_LEGACY_64B_CONTEXT << GEN8_CTX_ADDRESSING_MODE_SHIFT;
bool has_flat_ccs;
bool has_4tile;
bool has_range_tlb_invalidation;
+ bool has_asid;
};
#define PLATFORM(x) \
.max_tiles = 2,
.vm_max_level = 4,
.supports_usm = true,
+ .has_asid = true,
};
#define MTL_MEDIA_ENGINES \
xe->info.vm_max_level = desc->vm_max_level;
xe->info.media_ver = desc->media_ver;
xe->info.supports_usm = desc->supports_usm;
+ xe->info.has_asid = desc->has_asid;
xe->info.has_flat_ccs = desc->has_flat_ccs;
xe->info.has_4tile = desc->has_4tile;
xe->info.has_range_tlb_invalidation = desc->has_range_tlb_invalidation;
xe_device_mem_access_put(xe);
xe_pm_runtime_put(xe);
- if (xe->info.supports_usm) {
+ if (xe->info.has_asid) {
mutex_lock(&xe->usm.lock);
lookup = xa_erase(&xe->usm.asid_to_vm, vm->usm.asid);
XE_WARN_ON(lookup != vm);
return err;
}
- if (xe->info.supports_usm) {
+ if (xe->info.has_asid) {
mutex_lock(&xe->usm.lock);
err = xa_alloc_cyclic(&xe->usm.asid_to_vm, &asid, vm,
XA_LIMIT(0, XE_MAX_ASID - 1),