target-microblaze: Introduce a use-msr-instr property

Introduce a use-msr-instr property making msr instructions
optional.

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 70e47437f0dc3a00e6c54351f9febe702588305a..bc965055ab7126e39dafc60cd48ef667766f09b2 100644 (file)
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -157,7 +157,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         | PVR2_D_LMB_MASK \
                         | PVR2_I_OPB_MASK \
                         | PVR2_I_LMB_MASK \
-                        | PVR2_USE_MSR_INSTR \
                         | PVR2_USE_PCMP_INSTR \
                         | PVR2_FPU_EXC_MASK \
                         | 0;
@@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
                         (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
                         (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
-                        (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0);
+                        (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
+                        (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0);
 
     env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
                                         PVR5_DCACHE_WRITEBACK_MASK : 0;
@@ -241,6 +241,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
     DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
     DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
+    DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e202229c089c08cdedebeb6da6655b125d5e0e8a..5c960d01d310834c5e0fbbb233bb93c0a06070d4 100644 (file)
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -301,6 +301,7 @@ struct MicroBlazeCPU {
         uint8_t use_hw_mul;
         bool use_barrel;
         bool use_div;
+        bool use_msr_instr;
         bool use_mmu;
         bool dcache_writeback;
         bool endi;

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 36caa037ec44475fea484fc852ebc6b164bc5352..bb1bdfa5837a01a2f4442e42fb451d92a2ec583b 100644 (file)
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -443,7 +443,7 @@ static void dec_msr(DisasContext *dc)
         LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
                 dc->rd, dc->imm);
 
-        if (!(dc->cpu->env.pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
+        if (!dc->cpu->cfg.use_msr_instr) {
             /* nop??? */
             return;
         }