arm64: zynqmp: Wire qspi on multiple boards

Couple of boards have qspi on the board that's why enable controller and
describe them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/01a69ee6590245b5bee70a2553f6faac0d31ca76.1623684253.git.michal.simek@xilinx.com

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
index 2e05fa41695590dbaecebd964d05bea6d73acbb2..f1598527e5eccbdca3d6ddbb46fdcc532a2deb4d 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZC1232
  *
- * (C) Copyright 2017 - 2019, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
@@ -19,6 +19,7 @@
        aliases {
                serial0 = &uart0;
                serial1 = &dcc;
+               spi0 = &qspi;
        };
 
        chosen {
@@ -36,6 +37,19 @@
        status = "okay";
 };
 
+&qspi {
+       status = "okay";
+       flash@0 {
+               compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>;
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+       };
+};
+
 &sata {
        status = "okay";
        /* SATA OOB timing settings */

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
index 3d0aaa02f184f603f782b1a838f5bca876b40e88..04efa1683eaa918a249dd056a0302d40487ab5aa 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZC1254
  *
- * (C) Copyright 2015 - 2019, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@@ -20,6 +20,7 @@
        aliases {
                serial0 = &uart0;
                serial1 = &dcc;
+               spi0 = &qspi;
        };
 
        chosen {
@@ -37,6 +38,19 @@
        status = "okay";
 };
 
+&qspi {
+       status = "okay";
+       flash@0 {
+               compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+       };
+};
+
 &uart0 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
index cd406947ec34c47d7701c338770412e6995961af..9f176307b62a20342bb90c6c65a260ee92db082c 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
@@ -26,6 +26,7 @@
                mmc1 = &sdhci1;
                rtc0 = &rtc;
                serial0 = &uart0;
+               spi0 = &qspi;
        };
 
        chosen {
@@ -339,6 +340,19 @@
        };
 };
 
+&qspi {
+       status = "okay";
+       flash@0 {
+               compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>;
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+       };
+};
+
 &rtc {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
index 8046f0df0f35311ba70ed6fa446dd3f982c78026..05a2b79738afb41dd8b3ff3d6935d0877d288093 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
@@ -26,6 +26,7 @@
                rtc0 = &rtc;
                serial0 = &uart0;
                serial1 = &uart1;
+               spi0 = &qspi;
        };
 
        chosen {
@@ -161,6 +162,19 @@
        status = "okay";
 };
 
+&qspi {
+       status = "okay";
+       flash@0 {
+               compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>; /* also DUAL configuration possible */
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+       };
+};
+
 &rtc {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index 3cbc51b4587d88af1f2cb6a0acf6dde88e739a87..becfc23a561041fe4050fbd59584d109e9699dff 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -30,6 +30,7 @@
                serial0 = &uart0;
                serial1 = &uart1;
                serial2 = &dcc;
+               spi0 = &qspi;
        };
 
        chosen {
@@ -934,6 +935,20 @@
        clock-names = "ref0", "ref1", "ref2", "ref3";
 };
 
+&qspi {
+       status = "okay";
+       is-dual = <1>;
+       flash@0 {
+               compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+       };
+};
+
 &rtc {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
index 4c328569c3ac04e0be04a496c35c6a21ffcfcde0..84c4a9003e2e6ac3bd13348297d3851b7de8aa87 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -28,6 +28,7 @@
                serial0 = &uart0;
                serial1 = &uart1;
                serial2 = &dcc;
+               spi0 = &qspi;
        };
 
        chosen {
@@ -427,6 +428,19 @@
        clock-names = "ref1", "ref2", "ref3";
 };
 
+&qspi {
+       status = "okay";
+       flash@0 {
+               compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>;
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+       };
+};
+
 &sata {
        status = "okay";
        /* SATA OOB timing settings */

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
index 99d172867f6a790b03ff8af9eb04fb276edf9bae..fb8d76b5c27fff736cc5295325e8b86ea5e31ffb 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
@@ -28,6 +28,7 @@
                serial0 = &uart0;
                serial1 = &uart1;
                serial2 = &dcc;
+               spi0 = &qspi;
        };
 
        chosen {
@@ -435,6 +436,9 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>;
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
        };
 };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
index 464a76a13c24452e11aaf542b929922960c10221..d2219373580a5e6f5d8b6cfadf7e234e149f0bf7 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -30,6 +30,7 @@
                serial0 = &uart0;
                serial1 = &uart1;
                serial2 = &dcc;
+               spi0 = &qspi;
        };
 
        chosen {
@@ -928,6 +929,20 @@
        clock-names = "ref1", "ref2", "ref3";
 };
 
+&qspi {
+       status = "okay";
+       is-dual = <1>;
+       flash@0 {
+               compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+       };
+};
+
 &rtc {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
index c9d41d16c3f082418f4772d2f9ac9016e3fed7ed..4dc315ee91b730e802c535435a69f4abf5887deb 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -29,6 +29,7 @@
                rtc0 = &rtc;
                serial0 = &uart0;
                serial1 = &dcc;
+               spi0 = &qspi;
        };
 
        chosen {
@@ -772,6 +773,20 @@
        clock-names = "ref1", "ref2", "ref3";
 };
 
+&qspi {
+       status = "okay";
+       is-dual = <1>;
+       flash@0 {
+               compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+       };
+};
+
 &rtc {
        status = "okay";
 };