u8 addr;
 };
 
-static struct iwl_causes_list causes_list[] = {
+static const struct iwl_causes_list causes_list_common[] = {
        {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
        {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
        {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
        {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
        {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
        {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
-       {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
        {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
        {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
        {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
        {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
 };
 
+static const struct iwl_causes_list causes_list_pre_bz[] = {
+       {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
+};
+
+static const struct iwl_causes_list causes_list_bz[] = {
+       {MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ,      CSR_MSIX_HW_INT_MASK_AD, 0x29},
+};
+
+static void iwl_pcie_map_list(struct iwl_trans *trans,
+                             const struct iwl_causes_list *causes,
+                             int arr_size, int val)
+{
+       int i;
+
+       for (i = 0; i < arr_size; i++) {
+               iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
+               iwl_clear_bit(trans, causes[i].mask_reg,
+                             causes[i].cause_num);
+       }
+}
+
 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
 {
        struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
        int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
-       int i, arr_size = ARRAY_SIZE(causes_list);
-       struct iwl_causes_list *causes = causes_list;
-
        /*
         * Access all non RX causes and map them to the default irq.
         * In case we are missing at least one interrupt vector,
         * the first interrupt vector will serve non-RX and FBQ causes.
         */
-       for (i = 0; i < arr_size; i++) {
-               iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
-               iwl_clear_bit(trans, causes[i].mask_reg,
-                             causes[i].cause_num);
-       }
+       iwl_pcie_map_list(trans, causes_list_common,
+                         ARRAY_SIZE(causes_list_common), val);
+       if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
+               iwl_pcie_map_list(trans, causes_list_bz,
+                                 ARRAY_SIZE(causes_list_bz), val);
+       else
+               iwl_pcie_map_list(trans, causes_list_pre_bz,
+                                 ARRAY_SIZE(causes_list_pre_bz), val);
 }
 
 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
 
        if (trans_pcie->msix_enabled) {
                inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
-               sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
+               if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
+                       sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ;
+               else
+                       sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
        } else {
                inta_addr = CSR_INT;
                sw_err_bit = CSR_INT_BIT_SW_ERR;