*/
 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 {
-#define AR9462_BB_CTX_COEFJ(x) \
-               ar9462_##x##_baseband_core_txfir_coeff_japan_2484
-
-#define AR9462_BBC_TXIFR_COEFFJ \
-               ar9462_2p0_baseband_core_txfir_coeff_japan_2484
-
        if (AR_SREV_9330_11(ah)) {
                /* mac */
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
                INIT_INI_ARRAY(&ah->iniModesTxGain,
                                ar9331_modes_lowest_ob_db_tx_gain_1p1);
 
+               /* Japan 2484 Mhz CCK */
+               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+                              ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
+
                /* additional clock settings */
                if (ah->is_clk_25mhz)
                        INIT_INI_ARRAY(&ah->iniAdditional,
                INIT_INI_ARRAY(&ah->iniModesTxGain,
                                ar9331_modes_lowest_ob_db_tx_gain_1p2);
 
+               /* Japan 2484 Mhz CCK */
+               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+                              ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
+
                /* additional clock settings */
                if (ah->is_clk_25mhz)
                        INIT_INI_ARRAY(&ah->iniAdditional,
                INIT_INI_ARRAY(&ah->iniModesTxGain,
                                ar9485_modes_lowest_ob_db_tx_gain_1_1);
 
+               /* Japan 2484 Mhz CCK */
+               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+                              ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
+
                /* Load PCIE SERDES settings from INI */
 
                /* Awake Setting */
                                ar9462_modes_fast_clock_2p0);
 
                INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
-                               AR9462_BB_CTX_COEFJ(2p0));
-
-               INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);
+                              ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
        } else if (AR_SREV_9550(ah)) {
                /* mac */
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 
        REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
 
        if (chan->channel == 2484)
-               ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);
+               ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
 
        if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
                REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,