clk: renesas: r9a07g044: Add MTU3a clock and reset entry

Add MTU3a clock and reset entry to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221005111855.553436-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 02a4fc41bb6e1175b44fab19986356bb428879da..12b1a83625cb90cd251570e7a33191c08330b60b 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -182,7 +182,7 @@ static const struct {
 };
 
 static const struct {
-       struct rzg2l_mod_clk common[76];
+       struct rzg2l_mod_clk common[77];
 #ifdef CONFIG_CLK_R9A07G054
        struct rzg2l_mod_clk drp[0];
 #endif
@@ -204,6 +204,8 @@ static const struct {
                                        0x534, 1),
                DEF_MOD("ostm2_pclk",   R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
                                        0x534, 2),
+               DEF_MOD("mtu_x_mck",    R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
+                                       0x538, 0),
                DEF_MOD("gpt_pclk",     R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
                                        0x540, 0),
                DEF_MOD("poeg_a_clkp",  R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
@@ -356,6 +358,7 @@ static struct rzg2l_reset r9a07g044_resets[] = {
        DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
        DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
        DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
+       DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
        DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
        DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
        DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),