drm/i915/mtl: Fix PSR2_MAN_TRK_CTL bit getter functions for MTL
authorJouni Högander <jouni.hogander@intel.com>
Tue, 1 Nov 2022 11:53:42 +0000 (13:53 +0200)
committerJosé Roberto de Souza <jose.souza@intel.com>
Tue, 1 Nov 2022 20:03:06 +0000 (13:03 -0700)
MTL shares PSR2_MAN_TRK_CTL bits with ADL. Currently some bit
getter functions are incorrect for MTL. This patch fixes those.

Bspec: 49274

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221101115342.1136720-1-jouni.hogander@intel.com
drivers/gpu/drm/i915/display/intel_psr.c

index 564d4fd94048c98d2f16986785a2a04f4fe14c50..e11b0592055fb0e5a68da8d175054bbb2f457458 100644 (file)
@@ -1470,7 +1470,8 @@ unlock:
 
 static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv)
 {
-       return IS_ALDERLAKE_P(dev_priv) ? 0 : PSR2_MAN_TRK_CTL_ENABLE;
+       return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 0 :
+               PSR2_MAN_TRK_CTL_ENABLE;
 }
 
 static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv)
@@ -1482,14 +1483,14 @@ static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_pr
 
 static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv)
 {
-       return IS_ALDERLAKE_P(dev_priv) ?
+       return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ?
               ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
               PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
 }
 
 static u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv)
 {
-       return IS_ALDERLAKE_P(dev_priv) ?
+       return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ?
               ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
               PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
 }