return 0;
}
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
return 0;
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
return 0;
}
}
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
static int pmp(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = riscv_cpu_get_fflags(env);
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = env->frm;
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->rdtime_fn() + delta;
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = (env->rdtime_fn() + delta) >> 32;
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->mcounteren;
return 0;
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mcounteren = val;
return 0;
}
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
} else {
*val = env->satp;
}
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
{
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
} else {
if((val ^ env->satp) & SATP_ASID) {
tlb_flush(env_cpu(env));
static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#if defined(TARGET_RISCV32)
static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#if defined(TARGET_RISCV32)
static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->htimedelta >> 32;
static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
if ((write_mask && read_only) ||
(!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
/* ensure the CSR extension is enabled. */
if (!cpu->cfg.ext_icsr) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* check predicate */
if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* execute combined read/write operation if it exists */
/* if no accessor exists then return failure */
if (!csr_ops[csrno].read) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* read old value */
target_ulong csr)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, src, -1);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}