drm/xe/xe2: Add one more bit to encode PAT to ppgtt entries
authorLucas De Marchi <lucas.demarchi@intel.com>
Fri, 6 Oct 2023 18:23:23 +0000 (11:23 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 21 Dec 2023 16:42:57 +0000 (11:42 -0500)
Xe2 adds one more bit to cover all the possible 32 entries. Although
those entries are not used by internal kernel code paths, it's expected
that userspace will make use of it.

Bspec: 59510, 67095
Reviewed-by: Pallavi Mishra <pallavi.mishra@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231006182325.3617685-2-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/xe_bo.h
drivers/gpu/drm/xe/xe_vm.c

index 5666fd6d7f11c615c3a0ee9d331f8293689ecaa8..ba6ffd359ff70f6d91095f4a1d2a4d0ca7f1168e 100644 (file)
@@ -49,6 +49,7 @@
 #define XE_BO_INTERNAL_64K             BIT(31)
 
 #define XELPG_PPGTT_PTE_PAT3           BIT_ULL(62)
+#define XE2_PPGTT_PTE_PAT4             BIT_ULL(61)
 #define XE_PPGTT_PTE_PAT2              BIT_ULL(7)
 #define XE_PPGTT_PTE_PAT1              BIT_ULL(4)
 #define XE_PPGTT_PTE_PAT0              BIT_ULL(3)
index 10ed72228946b535a2518780df2c1fdf59efb7d5..665af2646243a694ea070059ca672d3bd5b07ffd 100644 (file)
@@ -1242,6 +1242,9 @@ static u64 pte_encode_cache(struct xe_device *xe, enum xe_cache_level cache)
        if (pat_index & BIT(3))
                pte |= XELPG_PPGTT_PTE_PAT3;
 
+       if (pat_index & (BIT(4)))
+               pte |= XE2_PPGTT_PTE_PAT4;
+
        return pte;
 }