wifi: rtw89: pci: generalize code of PCI control DMA IO for WiFi 7
authorPing-Ke Shih <pkshih@realtek.com>
Thu, 26 Oct 2023 12:00:49 +0000 (20:00 +0800)
committerKalle Valo <kvalo@kernel.org>
Mon, 30 Oct 2023 17:23:01 +0000 (19:23 +0200)
The register to enable/disable PCI DMA IO has many variants, so define
and use a field to control it accordingly.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231026120049.9187-5-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/pci.c
drivers/net/wireless/realtek/rtw89/pci.h
drivers/net/wireless/realtek/rtw89/rtw8851be.c
drivers/net/wireless/realtek/rtw89/rtw8852ae.c
drivers/net/wireless/realtek/rtw89/rtw8852be.c
drivers/net/wireless/realtek/rtw89/rtw8852ce.c
drivers/net/wireless/realtek/rtw89/rtw8922ae.c

index 13775c36a46b979cdb93e7b6dbab6fe07252f781..b2de5280d93425d89cd65a4cbc86a83f5fea7dc8 100644 (file)
@@ -1750,21 +1750,13 @@ static void rtw89_pci_ctrl_dma_trx(struct rtw89_dev *rtwdev, bool enable)
 
 static void rtw89_pci_ctrl_dma_io(struct rtw89_dev *rtwdev, bool enable)
 {
-       enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
-       u32 reg, mask;
-
-       if (chip_id == RTL8852C) {
-               reg = R_AX_HAXI_INIT_CFG1;
-               mask = B_AX_STOP_AXI_MST;
-       } else {
-               reg = R_AX_PCIE_DMA_STOP1;
-               mask = B_AX_STOP_PCIEIO;
-       }
+       const struct rtw89_pci_info *info = rtwdev->pci_info;
+       const struct rtw89_reg_def *reg = &info->dma_io_stop;
 
        if (enable)
-               rtw89_write32_clr(rtwdev, regmask);
+               rtw89_write32_clr(rtwdev, reg->addr, reg->mask);
        else
-               rtw89_write32_set(rtwdev, regmask);
+               rtw89_write32_set(rtwdev, reg->addr, reg->mask);
 }
 
 static void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable)
index e16507a5ec5a25ace33a8f526894158188a3d83d..fe1019ae5e5b9d396a4aead0d8abb073dc1daddc 100644 (file)
@@ -947,6 +947,7 @@ struct rtw89_pci_info {
        u32 max_tag_num_mask;
        u32 rxbd_rwptr_clr_reg;
        u32 txbd_rwptr_clr2_reg;
+       struct rtw89_reg_def dma_io_stop;
        struct rtw89_reg_def dma_stop1;
        struct rtw89_reg_def dma_stop2;
        struct rtw89_reg_def dma_busy1;
index 0f7711c50bd155e1f264ee3f20b1c9648d7365ec..3b299778119af9a9e8c4bc62818a03e965df49cb 100644 (file)
@@ -33,6 +33,7 @@ static const struct rtw89_pci_info rtw8851b_pci_info = {
        .max_tag_num_mask       = B_AX_MAX_TAG_NUM,
        .rxbd_rwptr_clr_reg     = R_AX_RXBD_RWPTR_CLR,
        .txbd_rwptr_clr2_reg    = 0,
+       .dma_io_stop            = {R_AX_PCIE_DMA_STOP1, B_AX_STOP_PCIEIO},
        .dma_stop1              = {R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_MASK_V1},
        .dma_stop2              = {0},
        .dma_busy1              = {R_AX_PCIE_DMA_BUSY1, DMA_BUSY1_CHECK_V1},
index 5895a7019375d9829a1c414688e804b57f121993..a40e87405dc8bfab458b3aeae86a30b1e3b43b76 100644 (file)
@@ -34,6 +34,7 @@ static const struct rtw89_pci_info rtw8852a_pci_info = {
        .max_tag_num_mask       = B_AX_MAX_TAG_NUM,
        .rxbd_rwptr_clr_reg     = R_AX_RXBD_RWPTR_CLR,
        .txbd_rwptr_clr2_reg    = R_AX_TXBD_RWPTR_CLR2,
+       .dma_io_stop            = {R_AX_PCIE_DMA_STOP1, B_AX_STOP_PCIEIO},
        .dma_stop1              = {R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_MASK},
        .dma_stop2              = {R_AX_PCIE_DMA_STOP2, B_AX_TX_STOP2_ALL},
        .dma_busy1              = {R_AX_PCIE_DMA_BUSY1, DMA_BUSY1_CHECK},
index 626a00dcddb69539341fdbddd78083de0e7b709b..9500ff9bb4aac3e826065f4ff79760dbc998b873 100644 (file)
@@ -34,6 +34,7 @@ static const struct rtw89_pci_info rtw8852b_pci_info = {
        .max_tag_num_mask       = B_AX_MAX_TAG_NUM,
        .rxbd_rwptr_clr_reg     = R_AX_RXBD_RWPTR_CLR,
        .txbd_rwptr_clr2_reg    = 0,
+       .dma_io_stop            = {R_AX_PCIE_DMA_STOP1, B_AX_STOP_PCIEIO},
        .dma_stop1              = {R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_MASK_V1},
        .dma_stop2              = {0},
        .dma_busy1              = {R_AX_PCIE_DMA_BUSY1, DMA_BUSY1_CHECK_V1},
index 5d34e56d9106a1aaf1bf7f335e9ee0ebdcfd2761..5c84589fd50e1ec956543bc92d26fcdfe1914850 100644 (file)
@@ -43,6 +43,7 @@ static const struct rtw89_pci_info rtw8852c_pci_info = {
        .max_tag_num_mask       = B_AX_MAX_TAG_NUM_V1_MASK,
        .rxbd_rwptr_clr_reg     = R_AX_RXBD_RWPTR_CLR_V1,
        .txbd_rwptr_clr2_reg    = R_AX_TXBD_RWPTR_CLR2_V1,
+       .dma_io_stop            = {R_AX_HAXI_INIT_CFG1, B_AX_STOP_AXI_MST},
        .dma_stop1              = {R_AX_HAXI_DMA_STOP1, B_AX_TX_STOP1_MASK},
        .dma_stop2              = {R_AX_HAXI_DMA_STOP2, B_AX_TX_STOP2_ALL},
        .dma_busy1              = {R_AX_HAXI_DMA_BUSY1, DMA_BUSY1_CHECK},
index c0c720daece1501756540df6bf6ceabe8fe93ed2..e55f25bafc6e7baf548d359a273a8dae665bdd01 100644 (file)
@@ -33,6 +33,7 @@ static const struct rtw89_pci_info rtw8922a_pci_info = {
        .max_tag_num_mask       = B_BE_MAX_TAG_NUM_MASK,
        .rxbd_rwptr_clr_reg     = R_BE_RXBD_RWPTR_CLR1_V1,
        .txbd_rwptr_clr2_reg    = R_BE_TXBD_RWPTR_CLR1,
+       .dma_io_stop            = {R_BE_HAXI_INIT_CFG1, B_BE_STOP_AXI_MST},
        .dma_stop1              = {R_BE_HAXI_DMA_STOP1, B_BE_TX_STOP1_MASK},
        .dma_stop2              = {0},
        .dma_busy1              = {R_BE_HAXI_DMA_BUSY1, DMA_BUSY1_CHECK_BE},