cpufreq: intel_pstate: Add one more OOB control bit

Add one more bit for OOB (Out Of Band) enabling of P-states.

If OOB handling of P-states is enabled, intel_pstate shouldn't load.
Currently, only "BIT(8) == 1" of the MSR MSR_MISC_PWR_MGMT is
considered as OOB, but "BIT(18) == 1" needs to be taken into
consideration as OOB condition too.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
[ rjw: Add an empty code line, edit subject and changelog ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 8e23a698ce048b92fdecfb25b6eda72e5437365b..e771e8b4f99f09cd93310eb4f32c933f2ab70e28 100644 (file)
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -2677,6 +2677,8 @@ static struct acpi_platform_list plat_info[] __initdata = {
        { } /* End */
 };
 
+#define BITMASK_OOB    (BIT(8) | BIT(18))
+
 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
 {
        const struct x86_cpu_id *id;
@@ -2686,8 +2688,9 @@ static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
        id = x86_match_cpu(intel_pstate_cpu_oob_ids);
        if (id) {
                rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
-               if (misc_pwr & (1 << 8)) {
-                       pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n");
+               if (misc_pwr & BITMASK_OOB) {
+                       pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
+                       pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
                        return true;
                }
        }