staging: rtl8723bs: checkpatch - fix typos in comments

Resolving checkpatch issue:
CHECK: 'Regsiter' may be misspelled - perhaps 'Register'?
CHECK: 'Interrup' may be misspelled - perhaps 'Interrupt'?

All instances resolved.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h
index 1f275a734ea79cbacf9d348f72ee825ff1652db5..1906ff2038f533d34b563cd13f717988800057c2 100644 (file)
--- a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h
+++ b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h
@@ -141,7 +141,7 @@
 #define SDIO_REG_HCPWM1_8723B  0x025 /*  HCI Current Power Mode 1 */
 
 /*  */
-/*     8723 Regsiter Bit and Content definition */
+/*     8723 Register Bit and Content definition */
 /*  */
 
 /* 2 HSISR */
@@ -241,13 +241,13 @@
 #define        IMR_BCNDMAINT3_8723B                            BIT23           /*  Beacon DMA Interrupt 3 */
 #define        IMR_BCNDMAINT2_8723B                            BIT22           /*  Beacon DMA Interrupt 2 */
 #define        IMR_BCNDMAINT1_8723B                            BIT21           /*  Beacon DMA Interrupt 1 */
-#define        IMR_BCNDOK7_8723B                                       BIT20           /*  Beacon Queue DMA OK Interrup 7 */
-#define        IMR_BCNDOK6_8723B                                       BIT19           /*  Beacon Queue DMA OK Interrup 6 */
-#define        IMR_BCNDOK5_8723B                                       BIT18           /*  Beacon Queue DMA OK Interrup 5 */
-#define        IMR_BCNDOK4_8723B                                       BIT17           /*  Beacon Queue DMA OK Interrup 4 */
-#define        IMR_BCNDOK3_8723B                                       BIT16           /*  Beacon Queue DMA OK Interrup 3 */
-#define        IMR_BCNDOK2_8723B                                       BIT15           /*  Beacon Queue DMA OK Interrup 2 */
-#define        IMR_BCNDOK1_8723B                                       BIT14           /*  Beacon Queue DMA OK Interrup 1 */
+#define        IMR_BCNDOK7_8723B                                       BIT20           /*  Beacon Queue DMA OK Interrupt 7 */
+#define        IMR_BCNDOK6_8723B                                       BIT19           /*  Beacon Queue DMA OK Interrupt 6 */
+#define        IMR_BCNDOK5_8723B                                       BIT18           /*  Beacon Queue DMA OK Interrupt 5 */
+#define        IMR_BCNDOK4_8723B                                       BIT17           /*  Beacon Queue DMA OK Interrupt 4 */
+#define        IMR_BCNDOK3_8723B                                       BIT16           /*  Beacon Queue DMA OK Interrupt 3 */
+#define        IMR_BCNDOK2_8723B                                       BIT15           /*  Beacon Queue DMA OK Interrupt 2 */
+#define        IMR_BCNDOK1_8723B                                       BIT14           /*  Beacon Queue DMA OK Interrupt 1 */
 #define        IMR_ATIMEND_E_8723B                             BIT13           /*  ATIM Window End Extension for Win7 */
 #define        IMR_TXERR_8723B                                 BIT11           /*  Tx Error Flag Interrupt Status, write 1 clear. */
 #define        IMR_RXERR_8723B                                 BIT10           /*  Rx Error Flag INT Status, Write 1 clear */