drm/i915/dg2: add TRANS_DP2_CTL register definition

This register controls the DP 2.0 datapath.

Bspec: 69967
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/0d3529df4501c5dd8ad1da0b6dbaabcfa97510b4.1629735412.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce518ecd77cf33a2de1455c1b9b448f8b713d2e1..9498852c14dd9172df44ee45bf880b72b50efcf0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9097,6 +9097,15 @@ enum {
 #define  TRANS_DP_HSYNC_ACTIVE_LOW     0
 #define  TRANS_DP_SYNC_MASK    (3 << 3)
 
+#define _TRANS_DP2_CTL_A                       0x600a0
+#define _TRANS_DP2_CTL_B                       0x610a0
+#define _TRANS_DP2_CTL_C                       0x620a0
+#define _TRANS_DP2_CTL_D                       0x630a0
+#define TRANS_DP2_CTL(trans)                   _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
+#define  TRANS_DP2_128B132B_CHANNEL_CODING     REG_BIT(31)
+#define  TRANS_DP2_PANEL_REPLAY_ENABLE         REG_BIT(30)
+#define  TRANS_DP2_DEBUG_ENABLE                        REG_BIT(23)
+
 /* SNB eDP training params */
 /* SNB A-stepping */
 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A                (0x38 << 22)