x86/cpu: Use common topology code for Centaur and Zhaoxin

Centaur and Zhaoxin CPUs use only the legacy SMP detection. Remove the
invocations from their 32bit path and exclude them from the 64-bit call
path.

No functional change intended.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Tested-by: Sohil Mehta <sohil.mehta@intel.com>
Tested-by: Michael Kelley <mhklinux@outlook.com>
Tested-by: Zhang Rui <rui.zhang@intel.com>
Tested-by: Wang Wendy <wendy.wang@intel.com>
Tested-by: K Prateek Nayak <kprateek.nayak@amd.com>
Link: https://lore.kernel.org/r/20240212153624.706794189@linutronix.de

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 345f7d905db677291f7f8eb9b33b692263afe447..a3b55db35c9612151b69b2ef559d93897cabf727 100644 (file)
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -128,10 +128,6 @@ static void init_centaur(struct cpuinfo_x86 *c)
 #endif
        early_init_centaur(c);
        init_intel_cacheinfo(c);
-       detect_num_cpu_cores(c);
-#ifdef CONFIG_X86_32
-       detect_ht(c);
-#endif
 
        if (c->cpuid_level > 9) {
                unsigned int eax = cpuid_eax(10);

diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c
index b0ff1fc84a13da5badf197c95f2f0f84d53944de..bcaaeecaf1a6329f0965dd6b36c14c26287effe8 100644 (file)
--- a/arch/x86/kernel/cpu/topology_common.c
+++ b/arch/x86/kernel/cpu/topology_common.c
@@ -42,7 +42,7 @@ static unsigned int __maybe_unused parse_num_cores_legacy(struct cpuinfo_x86 *c)
        return eax.ncores + 1;
 }
 
-static void __maybe_unused parse_legacy(struct topo_scan *tscan)
+static void parse_legacy(struct topo_scan *tscan)
 {
        unsigned int cores, core_shift, smt_shift = 0;
        struct cpuinfo_x86 *c = tscan->c;
@@ -71,10 +71,8 @@ bool topo_is_converted(struct cpuinfo_x86 *c)
        /* Temporary until everything is converted over. */
        switch (boot_cpu_data.x86_vendor) {
        case X86_VENDOR_AMD:
-       case X86_VENDOR_CENTAUR:
        case X86_VENDOR_INTEL:
        case X86_VENDOR_HYGON:
-       case X86_VENDOR_ZHAOXIN:
                return false;
        default:
                /* Let all UP systems use the below */
@@ -132,6 +130,13 @@ static void parse_topology(struct topo_scan *tscan, bool early)
                return;
 
        tscan->ebx1_nproc_shift = get_count_order(ebx.nproc);
+
+       switch (c->x86_vendor) {
+       case X86_VENDOR_CENTAUR:
+       case X86_VENDOR_ZHAOXIN:
+               parse_legacy(tscan);
+               break;
+       }
 }
 
 static void topo_set_ids(struct topo_scan *tscan)

diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 415564a6523b6e601bd4e51ae7e66aa5906a72be..90eba7eb53357153d4ad700a79bf0e7c4f9670f3 100644 (file)
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -71,10 +71,6 @@ static void init_zhaoxin(struct cpuinfo_x86 *c)
 {
        early_init_zhaoxin(c);
        init_intel_cacheinfo(c);
-       detect_num_cpu_cores(c);
-#ifdef CONFIG_X86_32
-       detect_ht(c);
-#endif
 
        if (c->cpuid_level > 9) {
                unsigned int eax = cpuid_eax(10);