net/mlx5: Add ts_cqe_to_dest_cqn related bits

Add a bit in HCA capabilities layout to indicate if ts_cqe_to_dest_cqn is
supported.

In addition, add ts_cqe_to_dest_cqn field to SQ context, for driver to
set the actual CQN.

Signed-off-by: Eran Ben Elisha <eranbe@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 11c24fafd7f2dd193faeead6f7d5f13f46224814..632b9a61fda53a4b535dfd417c67e69d155f8dbd 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1261,7 +1261,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         ece_support[0x1];
        u8         reserved_at_a4[0x7];
        u8         log_max_srq[0x5];
-       u8         reserved_at_b0[0x10];
+       u8         reserved_at_b0[0x2];
+       u8         ts_cqe_to_dest_cqn[0x1];
+       u8         reserved_at_b3[0xd];
 
        u8         max_sgl_for_optimized_performance[0x8];
        u8         log_max_cq_sz[0x8];
@@ -3312,8 +3314,12 @@ struct mlx5_ifc_sqc_bits {
        u8         reserved_at_80[0x10];
        u8         hairpin_peer_vhca[0x10];
 
-       u8         reserved_at_a0[0x50];
+       u8         reserved_at_a0[0x20];
 
+       u8         reserved_at_c0[0x8];
+       u8         ts_cqe_to_dest_cqn[0x18];
+
+       u8         reserved_at_e0[0x10];
        u8         packet_pacing_rate_limit_index[0x10];
        u8         tis_lst_sz[0x10];
        u8         reserved_at_110[0x10];