soc: ti: omap-prm: dra7: add genpd support for remaining PRM instances

Add genpd support for mpu, dsp, ipu, coreaon, core, iva, cam, dss, gpu,
l3init, l4per, custefuse, wkupaon, emu, eve, rtc and vpe instances.

Cc: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c
index 408cc4406a554a12507aa5d0167d204aa29bc846..dd211cb5fbd3cdcf6ef025bc2df04470d64463a8 100644 (file)
--- a/drivers/soc/ti/omap_prm.c
+++ b/drivers/soc/ti/omap_prm.c
@@ -234,15 +234,103 @@ static const struct omap_prm_data omap5_prm_data[] = {
 };
 
 static const struct omap_prm_data dra7_prm_data[] = {
-       { .name = "dsp1", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
-       { .name = "ipu", .base = 0x4ae06500, .rstctrl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1", .rstmap = rst_map_012 },
-       { .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu2", .rstmap = rst_map_012 },
-       { .name = "iva", .base = 0x4ae06f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
-       { .name = "dsp2", .base = 0x4ae07b00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
-       { .name = "eve1", .base = 0x4ae07b40, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
-       { .name = "eve2", .base = 0x4ae07b80, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
-       { .name = "eve3", .base = 0x4ae07bc0, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
-       { .name = "eve4", .base = 0x4ae07c00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
+       {
+               .name = "mpu", .base = 0x4ae06300,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
+       },
+       {
+               .name = "dsp1", .base = 0x4ae06400,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+               .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01,
+       },
+       {
+               .name = "ipu", .base = 0x4ae06500,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+               .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
+               .clkdm_name = "ipu1"
+       },
+       {
+               .name = "coreaon", .base = 0x4ae06628,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
+       },
+       {
+               .name = "core", .base = 0x4ae06700,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
+               .rstctrl = 0x210, .rstst = 0x214, .rstmap = rst_map_012,
+               .clkdm_name = "ipu2"
+       },
+       {
+               .name = "iva", .base = 0x4ae06f00,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+               .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
+       },
+       {
+               .name = "cam", .base = 0x4ae07000,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+       },
+       {
+               .name = "dss", .base = 0x4ae07100,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+       },
+       {
+               .name = "gpu", .base = 0x4ae07200,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+       },
+       {
+               .name = "l3init", .base = 0x4ae07300,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
+               .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
+               .clkdm_name = "pcie"
+       },
+       {
+               .name = "l4per", .base = 0x4ae07400,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
+       },
+       {
+               .name = "custefuse", .base = 0x4ae07600,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+       },
+       {
+               .name = "wkupaon", .base = 0x4ae07724,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
+       },
+       {
+               .name = "emu", .base = 0x4ae07900,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+       },
+       {
+               .name = "dsp2", .base = 0x4ae07b00,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+               .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
+       },
+       {
+               .name = "eve1", .base = 0x4ae07b40,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+               .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
+       },
+       {
+               .name = "eve2", .base = 0x4ae07b80,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+               .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
+       },
+       {
+               .name = "eve3", .base = 0x4ae07bc0,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+               .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
+       },
+       {
+               .name = "eve4", .base = 0x4ae07c00,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+               .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
+       },
+       {
+               .name = "rtc", .base = 0x4ae07c60,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
+       },
+       {
+               .name = "vpe", .base = 0x4ae07c80,
+               .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
+       },
        { },
 };