ARM: dts: r8a7742: Add CAN support

Add the definitions for can0 and can1 to the r8a7742 SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Link: https://lore.kernel.org/r/20200816190732.6905-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 009827708bf44ba0746aaa88922e86e9a2111b58..0fc52b27ae64956f1629c5b2bb741feb39e08588 100644 (file)
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -36,6 +36,14 @@
                clock-frequency = <0>;
        };
 
+       /* External CAN clock */
+       can_clk: can {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board. */
+               clock-frequency = <0>;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -951,6 +959,32 @@
                        status = "disabled";
                };
 
+               can0: can@e6e80000 {
+                       compatible = "renesas,can-r8a7742",
+                                    "renesas,rcar-gen2-can";
+                       reg = <0 0xe6e80000 0 0x1000>;
+                       interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 916>,
+                                <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
+                       clock-names = "clkp1", "clkp2", "can_clk";
+                       power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+                       resets = <&cpg 916>;
+                       status = "disabled";
+               };
+
+               can1: can@e6e88000 {
+                       compatible = "renesas,can-r8a7742",
+                                    "renesas,rcar-gen2-can";
+                       reg = <0 0xe6e88000 0 0x1000>;
+                       interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 915>,
+                                <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
+                       clock-names = "clkp1", "clkp2", "can_clk";
+                       power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+                       resets = <&cpg 915>;
+                       status = "disabled";
+               };
+
                pwm0: pwm@e6e30000 {
                        compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
                        reg = <0 0xe6e30000 0 0x8>;