drm:amdgpu: enable IH ring1 for IH v6.1

We need IH ring1 for handling the pagefault
interrupts which over flow in default
ring for specific usecases.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index b8da0fc29378c496ba0392e10105d1c58d53bf5a..73dba180fabde4dfb8e7da048f236ba0e435058b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -550,8 +550,15 @@ static int ih_v6_1_sw_init(void *handle)
        adev->irq.ih.use_doorbell = true;
        adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 
-       adev->irq.ih1.ring_size = 0;
-       adev->irq.ih2.ring_size = 0;
+       if (!(adev->flags & AMD_IS_APU)) {
+               r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE,
+                                       use_bus_addr);
+               if (r)
+                       return r;
+
+               adev->irq.ih1.use_doorbell = true;
+               adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
+       }
 
        /* initialize ih control register offset */
        ih_v6_1_init_register_offset(adev);