arm64: dts: renesas: r8a779g0: Add CPUIdle support

Support CPUIdle for ARM Cortex-A76 on R-Car V4H.

Based on patches in the BSP by Tho Vu and Vincent Bryce.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f6d4076983eb45cf23595a045747f28cbdcdf4e6.1668429870.git.geert+renesas@glider.be

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index dc5f27c114a7ad96130a6a7f0c7cb477cb93e7c4..21baa4936b4fba3e2153e0689e965f6f1adb71f8 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -45,6 +45,7 @@
                        power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
                        next-level-cache = <&L3_CA76_0>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
 
                a76_1: cpu@100 {
@@ -54,6 +55,7 @@
                        power-domains = <&sysc R8A779G0_PD_A1E0D0C1>;
                        next-level-cache = <&L3_CA76_0>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
 
                a76_2: cpu@10000 {
@@ -63,6 +65,7 @@
                        power-domains = <&sysc R8A779G0_PD_A1E0D1C0>;
                        next-level-cache = <&L3_CA76_1>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
 
                a76_3: cpu@10100 {
@@ -72,8 +75,22 @@
                        power-domains = <&sysc R8A779G0_PD_A1E0D1C1>;
                        next-level-cache = <&L3_CA76_1>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
 
+               idle-states {
+                       entry-method = "psci";
+
+                       CPU_SLEEP_0: cpu-sleep-0 {
+                               compatible = "arm,idle-state";
+                               arm,psci-suspend-param = <0x0010000>;
+                               local-timer-stop;
+                               entry-latency-us = <400>;
+                               exit-latency-us = <500>;
+                               min-residency-us = <4000>;
+                       };
+              };
+
                L3_CA76_0: cache-controller-0 {
                        compatible = "cache";
                        power-domains = <&sysc R8A779G0_PD_A2E0D0>;