The reason why PHYlib may access MII_CTRL1000 on the chip without GBit
support is only if chip provides wrong information about extended caps
register. This issue is now handled by ksz9477_r_phy_quirks()
With proper regmap_ranges provided for all chips we will be able to
catch this kind of bugs any way. So, remove this sanity check.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
if (addr >= dev->phy_port_cnt)
return 0;
- /* No gigabit support. Do not write to this register. */
- if (!dev->info->gbit_capable[addr] && reg == MII_CTRL1000)
- return -ENXIO;
-
return ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
}