drm/amdgpu: switch to common helper func for psp cmd submission

Drop all the IP specific cmd_submit callback function
and use the common helper instead

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 88fb04da602674efe1b295b3892dc53dc09a45a5..2a8a08aa6eaf86cb452563d6180f5a42367fcb08 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -158,7 +158,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
        memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 
        index = atomic_inc_return(&psp->fence_value);
-       ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
+       ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
        if (ret) {
                atomic_dec(&psp->fence_value);
                mutex_unlock(&psp->mutex);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 482e7675b7da4b50fd57b91fbffae5ddd20c808f..40594f27dab1fc96848a8acd9fcebed9fb9ee544 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -94,9 +94,6 @@ struct psp_funcs
                            enum psp_ring_type ring_type);
        int (*ring_destroy)(struct psp_context *psp,
                            enum psp_ring_type ring_type);
-       int (*cmd_submit)(struct psp_context *psp,
-                         uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
-                         int index);
        bool (*compare_sram_data)(struct psp_context *psp,
                                  struct amdgpu_firmware_info *ucode,
                                  enum AMDGPU_UCODE_ID ucode_type);
@@ -302,8 +299,6 @@ struct amdgpu_psp_funcs {
 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
-#define psp_cmd_submit(psp, cmd_mc, fence_mc, index) \
-               (psp)->funcs->cmd_submit((psp), (cmd_mc), (fence_mc), (index))
 #define psp_compare_sram_data(psp, ucode, type) \
                (psp)->funcs->compare_sram_data((psp), (ucode), (type))
 #define psp_init_microcode(psp) \

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 4b8fdddc4c4667139e2a8b0085e18fde31125c78..7539104175e8ae451520e618c4886b67f5d35e37 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -230,54 +230,6 @@ static int psp_v10_0_ring_destroy(struct psp_context *psp,
        return ret;
 }
 
-static int psp_v10_0_cmd_submit(struct psp_context *psp,
-                               uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
-                               int index)
-{
-       unsigned int psp_write_ptr_reg = 0;
-       struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
-       struct psp_ring *ring = &psp->km_ring;
-       struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
-       struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
-               ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
-       struct amdgpu_device *adev = psp->adev;
-       uint32_t ring_size_dw = ring->ring_size / 4;
-       uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
-
-       /* KM (GPCOM) prepare write pointer */
-       psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
-
-       /* Update KM RB frame pointer to new frame */
-       if ((psp_write_ptr_reg % ring_size_dw) == 0)
-               write_frame = ring_buffer_start;
-       else
-               write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
-       /* Check invalid write_frame ptr address */
-       if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
-               DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
-                         ring_buffer_start, ring_buffer_end, write_frame);
-               DRM_ERROR("write_frame is pointing to address out of bounds\n");
-               return -EINVAL;
-       }
-
-       /* Initialize KM RB frame */
-       memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
-
-       /* Update KM RB frame */
-       write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
-       write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
-       write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
-       write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
-       write_frame->fence_value = index;
-       amdgpu_asic_flush_hdp(adev, NULL);
-
-       /* Update the write Pointer in DWORDs */
-       psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
-
-       return 0;
-}
-
 static int
 psp_v10_0_sram_map(struct amdgpu_device *adev,
                   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
@@ -427,7 +379,6 @@ static const struct psp_funcs psp_v10_0_funcs = {
        .ring_create = psp_v10_0_ring_create,
        .ring_stop = psp_v10_0_ring_stop,
        .ring_destroy = psp_v10_0_ring_destroy,
-       .cmd_submit = psp_v10_0_cmd_submit,
        .compare_sram_data = psp_v10_0_compare_sram_data,
        .mode1_reset = psp_v10_0_mode1_reset,
        .ring_get_wptr = psp_v10_0_ring_get_wptr,

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 5cd2733aa2eaa452aa3ce248ffe7b735227237c2..2eaa197a94042c3a5a958d140a2e9b4ada1372a0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -519,63 +519,6 @@ static int psp_v11_0_ring_destroy(struct psp_context *psp,
        return ret;
 }
 
-static int psp_v11_0_cmd_submit(struct psp_context *psp,
-                              uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
-                              int index)
-{
-       unsigned int psp_write_ptr_reg = 0;
-       struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
-       struct psp_ring *ring = &psp->km_ring;
-       struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
-       struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
-               ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
-       struct amdgpu_device *adev = psp->adev;
-       uint32_t ring_size_dw = ring->ring_size / 4;
-       uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
-
-       /* KM (GPCOM) prepare write pointer */
-       if (psp_v11_0_support_vmr_ring(psp))
-               psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
-       else
-               psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
-
-       /* Update KM RB frame pointer to new frame */
-       /* write_frame ptr increments by size of rb_frame in bytes */
-       /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
-       if ((psp_write_ptr_reg % ring_size_dw) == 0)
-               write_frame = ring_buffer_start;
-       else
-               write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
-       /* Check invalid write_frame ptr address */
-       if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
-               DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
-                         ring_buffer_start, ring_buffer_end, write_frame);
-               DRM_ERROR("write_frame is pointing to address out of bounds\n");
-               return -EINVAL;
-       }
-
-       /* Initialize KM RB frame */
-       memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
-
-       /* Update KM RB frame */
-       write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
-       write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
-       write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
-       write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
-       write_frame->fence_value = index;
-       amdgpu_asic_flush_hdp(adev, NULL);
-
-       /* Update the write Pointer in DWORDs */
-       psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
-       if (psp_v11_0_support_vmr_ring(psp)) {
-               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
-               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
-       } else
-               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
-
-       return 0;
-}
-
 static int
 psp_v11_0_sram_map(struct amdgpu_device *adev,
                  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
@@ -1101,7 +1044,6 @@ static const struct psp_funcs psp_v11_0_funcs = {
        .ring_create = psp_v11_0_ring_create,
        .ring_stop = psp_v11_0_ring_stop,
        .ring_destroy = psp_v11_0_ring_destroy,
-       .cmd_submit = psp_v11_0_cmd_submit,
        .compare_sram_data = psp_v11_0_compare_sram_data,
        .mode1_reset = psp_v11_0_mode1_reset,
        .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
index 75b3f9d15a18733390071588f131e9f263bcc325..58d8b6d732e8f0b6e26fc52738dad013813c03e7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
@@ -334,63 +334,6 @@ static int psp_v12_0_ring_destroy(struct psp_context *psp,
        return ret;
 }
 
-static int psp_v12_0_cmd_submit(struct psp_context *psp,
-                              uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
-                              int index)
-{
-       unsigned int psp_write_ptr_reg = 0;
-       struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
-       struct psp_ring *ring = &psp->km_ring;
-       struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
-       struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
-               ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
-       struct amdgpu_device *adev = psp->adev;
-       uint32_t ring_size_dw = ring->ring_size / 4;
-       uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
-
-       /* KM (GPCOM) prepare write pointer */
-       if (psp_v12_0_support_vmr_ring(psp))
-               psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
-       else
-               psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
-
-       /* Update KM RB frame pointer to new frame */
-       /* write_frame ptr increments by size of rb_frame in bytes */
-       /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
-       if ((psp_write_ptr_reg % ring_size_dw) == 0)
-               write_frame = ring_buffer_start;
-       else
-               write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
-       /* Check invalid write_frame ptr address */
-       if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
-               DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
-                         ring_buffer_start, ring_buffer_end, write_frame);
-               DRM_ERROR("write_frame is pointing to address out of bounds\n");
-               return -EINVAL;
-       }
-
-       /* Initialize KM RB frame */
-       memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
-
-       /* Update KM RB frame */
-       write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
-       write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
-       write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
-       write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
-       write_frame->fence_value = index;
-       amdgpu_asic_flush_hdp(adev, NULL);
-
-       /* Update the write Pointer in DWORDs */
-       psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
-       if (psp_v12_0_support_vmr_ring(psp)) {
-               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
-               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
-       } else
-               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
-
-       return 0;
-}
-
 static int
 psp_v12_0_sram_map(struct amdgpu_device *adev,
                  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
@@ -579,7 +522,6 @@ static const struct psp_funcs psp_v12_0_funcs = {
        .ring_create = psp_v12_0_ring_create,
        .ring_stop = psp_v12_0_ring_stop,
        .ring_destroy = psp_v12_0_ring_destroy,
-       .cmd_submit = psp_v12_0_cmd_submit,
        .compare_sram_data = psp_v12_0_compare_sram_data,
        .mode1_reset = psp_v12_0_mode1_reset,
        .ring_get_wptr = psp_v12_0_ring_get_wptr,

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index bee6514f04a9b6694f706be6f3e6d2217552ca24..b4d6427aaa79f35476fb38b5bc1668aa22ebb87b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -410,65 +410,6 @@ static int psp_v3_1_ring_destroy(struct psp_context *psp,
        return ret;
 }
 
-static int psp_v3_1_cmd_submit(struct psp_context *psp,
-                              uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
-                              int index)
-{
-       unsigned int psp_write_ptr_reg = 0;
-       struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
-       struct psp_ring *ring = &psp->km_ring;
-       struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
-       struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
-               ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
-       struct amdgpu_device *adev = psp->adev;
-       uint32_t ring_size_dw = ring->ring_size / 4;
-       uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
-
-       /* KM (GPCOM) prepare write pointer */
-       if (psp_v3_1_support_vmr_ring(psp))
-               psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
-       else
-               psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
-
-       /* Update KM RB frame pointer to new frame */
-       /* write_frame ptr increments by size of rb_frame in bytes */
-       /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
-       if ((psp_write_ptr_reg % ring_size_dw) == 0)
-               write_frame = ring_buffer_start;
-       else
-               write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
-       /* Check invalid write_frame ptr address */
-       if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
-               DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
-                         ring_buffer_start, ring_buffer_end, write_frame);
-               DRM_ERROR("write_frame is pointing to address out of bounds\n");
-               return -EINVAL;
-       }
-
-       /* Initialize KM RB frame */
-       memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
-
-       /* Update KM RB frame */
-       write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
-       write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
-       write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
-       write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
-       write_frame->fence_value = index;
-       amdgpu_asic_flush_hdp(adev, NULL);
-
-       /* Update the write Pointer in DWORDs */
-       psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
-       if (psp_v3_1_support_vmr_ring(psp)) {
-               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
-               /* send interrupt to PSP for SRIOV ring write pointer update */
-               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
-                                       GFX_CTRL_CMD_ID_CONSUME_CMD);
-       } else
-               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
-
-       return 0;
-}
-
 static int
 psp_v3_1_sram_map(struct amdgpu_device *adev,
                  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
@@ -675,7 +616,6 @@ static const struct psp_funcs psp_v3_1_funcs = {
        .ring_create = psp_v3_1_ring_create,
        .ring_stop = psp_v3_1_ring_stop,
        .ring_destroy = psp_v3_1_ring_destroy,
-       .cmd_submit = psp_v3_1_cmd_submit,
        .compare_sram_data = psp_v3_1_compare_sram_data,
        .smu_reload_quirk = psp_v3_1_smu_reload_quirk,
        .mode1_reset = psp_v3_1_mode1_reset,