irqchip/irq-mtk-cirq: Add support for System CIRQ on MT8192

On some SoCs the System CIRQ register layout is slightly different,
as there are more registers per function and in some cases other
differences later in the layout: this is seen on at least MT8192,
but it's also valid for some other "contemporary" SoCs both for
Chromebooks and for smartphones.

Add the new "v2" register layout and use it if the compatible
"mediatek,mt8192-cirq" is found.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221128092217.36552-5-angelogioacchino.delregno@collabora.com

diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c
index 4776ed6492fbbbc5e29e0fb97d41299591ae0368..76bc0283e3b963798424deb960c8ccd5d52e068a 100644 (file)
--- a/drivers/irqchip/irq-mtk-cirq.c
+++ b/drivers/irqchip/irq-mtk-cirq.c
@@ -39,6 +39,18 @@ static const u32 mtk_cirq_regoffs_v1[] = {
        [CIRQ_CONTROL]  = 0x300,
 };
 
+static const u32 mtk_cirq_regoffs_v2[] = {
+       [CIRQ_STA]      = 0x0,
+       [CIRQ_ACK]      = 0x80,
+       [CIRQ_MASK_SET] = 0x180,
+       [CIRQ_MASK_CLR] = 0x200,
+       [CIRQ_SENS_SET] = 0x300,
+       [CIRQ_SENS_CLR] = 0x380,
+       [CIRQ_POL_SET]  = 0x480,
+       [CIRQ_POL_CLR]  = 0x500,
+       [CIRQ_CONTROL]  = 0x600,
+};
+
 #define CIRQ_EN        0x1
 #define CIRQ_EDGE      0x2
 #define CIRQ_FLUSH     0x4
@@ -277,6 +289,7 @@ static const struct of_device_id mtk_cirq_of_match[] = {
        { .compatible = "mediatek,mt2701-cirq", .data = &mtk_cirq_regoffs_v1 },
        { .compatible = "mediatek,mt8135-cirq", .data = &mtk_cirq_regoffs_v1 },
        { .compatible = "mediatek,mt8173-cirq", .data = &mtk_cirq_regoffs_v1 },
+       { .compatible = "mediatek,mt8192-cirq", .data = &mtk_cirq_regoffs_v2 },
        { /* sentinel */ }
 };