[IB_QPT_UC]     = WR_LOCAL_OP_MASK,
                },
        },
+       [IB_WR_ATOMIC_WRITE]                       = {
+               .name   = "IB_WR_ATOMIC_WRITE",
+               .mask   = {
+                       [IB_QPT_RC]     = WR_ATOMIC_WRITE_MASK,
+               },
+       },
 };
 
 struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE] = {
                                          RXE_IETH_BYTES,
                }
        },
+       [IB_OPCODE_RC_ATOMIC_WRITE]                        = {
+               .name   = "IB_OPCODE_RC_ATOMIC_WRITE",
+               .mask   = RXE_RETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK |
+                         RXE_ATOMIC_WRITE_MASK | RXE_START_MASK |
+                         RXE_END_MASK,
+               .length = RXE_BTH_BYTES + RXE_RETH_BYTES,
+               .offset = {
+                       [RXE_BTH]       = 0,
+                       [RXE_RETH]      = RXE_BTH_BYTES,
+                       [RXE_PAYLOAD]   = RXE_BTH_BYTES + RXE_RETH_BYTES,
+               }
+       },
 
        /* UC */
        [IB_OPCODE_UC_SEND_FIRST]                       = {
 
        WR_READ_MASK                    = BIT(3),
        WR_WRITE_MASK                   = BIT(4),
        WR_LOCAL_OP_MASK                = BIT(5),
+       WR_ATOMIC_WRITE_MASK            = BIT(7),
 
        WR_READ_OR_WRITE_MASK           = WR_READ_MASK | WR_WRITE_MASK,
        WR_WRITE_OR_SEND_MASK           = WR_WRITE_MASK | WR_SEND_MASK,
 
        RXE_LOOPBACK_MASK       = BIT(NUM_HDR_TYPES + 12),
 
+       RXE_ATOMIC_WRITE_MASK   = BIT(NUM_HDR_TYPES + 14),
+
        RXE_READ_OR_ATOMIC_MASK = (RXE_READ_MASK | RXE_ATOMIC_MASK),
        RXE_WRITE_OR_SEND_MASK  = (RXE_WRITE_MASK | RXE_SEND_MASK),
        RXE_READ_OR_WRITE_MASK  = (RXE_READ_MASK | RXE_WRITE_MASK),