drm/amd/pm: add SMU11 common deep sleep control interface

Considering the same logic can be applied to Arcturus, Navi1X
and Sienna Cichlid.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index c4743f8d0d230c717521e72785af3cd85baa7617..2a3f1ee4a50b07c7cbcfc8e88a20b07af54e4bca 100644 (file)
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -277,5 +277,8 @@ void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics);
 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
                              bool enablement);
 
+int smu_v11_0_deep_sleep_control(struct smu_context *smu,
+                                bool enablement);
+
 #endif
 #endif

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index aab83b9572464fb1ecf7e409ae1f78ae79956447..8347b1f2509fba963f81fdda003da88a7037d774 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -2392,6 +2392,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
        .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
        .get_gpu_metrics = arcturus_get_gpu_metrics,
        .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
+       .deep_sleep_control = smu_v11_0_deep_sleep_control,
 };
 
 void arcturus_set_ppt_funcs(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index c968f05533d9c2676f16d10ddea1b418293d7c98..72f3d68691d8d4852c75f6fe0abb9fa1028e643a 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2661,6 +2661,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
        .get_gpu_metrics = navi10_get_gpu_metrics,
        .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
        .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
+       .deep_sleep_control = smu_v11_0_deep_sleep_control,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 45b9defebd07a0b25075505e10bf6fbdbb08d75b..8ffa8b71b75fe4cb292b94324a3c60ad48a57c18 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -2797,6 +2797,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
        .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
        .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
        .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
+       .deep_sleep_control = smu_v11_0_deep_sleep_control,
 };
 
 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 3c98060e04b8b7affaa9eea395a564dcfb743372..ec20e839f555c817ed0782c3d2ad873a18fedce6 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1996,3 +1996,36 @@ int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
 
        return ret;
 }
+
+int smu_v11_0_deep_sleep_control(struct smu_context *smu,
+                                bool enablement)
+{
+       struct amdgpu_device *adev = smu->adev;
+       int ret = 0;
+
+       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
+               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
+               if (ret) {
+                       dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
+                       return ret;
+               }
+       }
+
+       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
+               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
+               if (ret) {
+                       dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
+                       return ret;
+               }
+       }
+
+       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
+               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
+               if (ret) {
+                       dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
+                       return ret;
+               }
+       }
+
+       return ret;
+}