drm/vc4: crtc: Remove the feed_txp tests

Now that the code in vc4_crtc accessing registers is only meant for the
pixelvalve, it doesn't make sense anymore to test whether we're accessing
the TXP or not and we can safely remove those checks.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/c044daba470fcb1cb57e3d34d88f75325b2ebbab.1591882579.git-series.maxime@cerno.tech

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 1a9c7a80f37f7faf188205af0b143e8a161c2ac9..6d8fa6118fc1a559585184977d31c26dae5e9052 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -323,7 +323,6 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 {
        struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
-       struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
        bool debug_dump_regs = false;
 
        if (debug_dump_regs) {
@@ -333,8 +332,7 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
                drm_print_regset32(&p, &vc4_crtc->regset);
        }
 
-       if (!vc4_state->feed_txp)
-               vc4_crtc_config_pv(crtc);
+       vc4_crtc_config_pv(crtc);
 
        vc4_hvs_mode_set_nofb(crtc);
 
@@ -357,7 +355,6 @@ static void require_hvs_enabled(struct drm_device *dev)
 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
                                    struct drm_crtc_state *old_state)
 {
-       struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
        struct drm_device *dev = crtc->dev;
        struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
        int ret;
@@ -367,12 +364,10 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
        /* Disable vblank irq handling before crtc is disabled. */
        drm_crtc_vblank_off(crtc);
 
-       if (!vc4_state->feed_txp) {
-               CRTC_WRITE(PV_V_CONTROL,
-                          CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
-               ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
-               WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
-       }
+       CRTC_WRITE(PV_V_CONTROL,
+                  CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
+       ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
+       WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 
        vc4_hvs_atomic_disable(crtc, old_state);
 
@@ -395,7 +390,6 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 {
        struct drm_device *dev = crtc->dev;
        struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
-       struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 
        require_hvs_enabled(dev);
 
@@ -409,9 +403,8 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
        /* When feeding the transposer block the pixelvalve is unneeded and
         * should not be enabled.
         */
-       if (!vc4_state->feed_txp)
-               CRTC_WRITE(PV_V_CONTROL,
-                          CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
+       CRTC_WRITE(PV_V_CONTROL,
+                  CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 }
 
 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
@@ -487,10 +480,6 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 static int vc4_enable_vblank(struct drm_crtc *crtc)
 {
        struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
-       struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
-
-       if (vc4_state->feed_txp)
-               return 0;
 
        CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 
@@ -500,10 +489,6 @@ static int vc4_enable_vblank(struct drm_crtc *crtc)
 static void vc4_disable_vblank(struct drm_crtc *crtc)
 {
        struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
-       struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
-
-       if (vc4_state->feed_txp)
-               return;
 
        CRTC_WRITE(PV_INTEN, 0);
 }