int feat;
int enabled;
qemu_irq irq;
-} sh_timer_state;
+} SHTimerState;
/* Check all active timers, and schedule the next timer interrupt. */
-static void sh_timer_update(sh_timer_state *s)
+static void sh_timer_update(SHTimerState *s)
{
int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
static uint32_t sh_timer_read(void *opaque, hwaddr offset)
{
- sh_timer_state *s = (sh_timer_state *)opaque;
+ SHTimerState *s = opaque;
switch (offset >> 2) {
case OFFSET_TCOR:
static void sh_timer_write(void *opaque, hwaddr offset,
uint32_t value)
{
- sh_timer_state *s = (sh_timer_state *)opaque;
+ SHTimerState *s = opaque;
int freq;
switch (offset >> 2) {
static void sh_timer_start_stop(void *opaque, int enable)
{
- sh_timer_state *s = (sh_timer_state *)opaque;
+ SHTimerState *s = opaque;
trace_sh_timer_start_stop(enable, s->enabled);
ptimer_transaction_begin(s->timer);
static void sh_timer_tick(void *opaque)
{
- sh_timer_state *s = (sh_timer_state *)opaque;
+ SHTimerState *s = opaque;
s->int_level = s->enabled;
sh_timer_update(s);
}
static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
{
- sh_timer_state *s;
+ SHTimerState *s;
s = g_malloc0(sizeof(*s));
s->freq = freq;
static uint64_t tmu012_read(void *opaque, hwaddr offset,
unsigned size)
{
- tmu012_state *s = (tmu012_state *)opaque;
+ tmu012_state *s = opaque;
trace_sh_timer_read(offset);
if (offset >= 0x20) {
static void tmu012_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
- tmu012_state *s = (tmu012_state *)opaque;
+ tmu012_state *s = opaque;
trace_sh_timer_write(offset, value);
if (offset >= 0x20) {