arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores

Complete the description of the Cortex-A76 CPU cores and L3 cache
controllers on the Renesas R-Car V4M (R8A779H0) SoC, including CPU
topology and PSCI support for enabling CPU cores.

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c2a38a0da74915bf2a9171e53886c83a1c732934.1706796979.git.geert+renesas@glider.be

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
index f47695158d991288ca9e0715afc5a1d12b9f825b..88c5dcbc38d59dabf5732d9f3877c592a5965ef6 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
@@ -18,12 +18,57 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&a76_0>;
+                               };
+                               core1 {
+                                       cpu = <&a76_1>;
+                               };
+                               core2 {
+                                       cpu = <&a76_2>;
+                               };
+                               core3 {
+                                       cpu = <&a76_3>;
+                               };
+                       };
+               };
+
                a76_0: cpu@0 {
                        compatible = "arm,cortex-a76";
                        reg = <0>;
                        device_type = "cpu";
                        power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
                        next-level-cache = <&L3_CA76>;
+                       enable-method = "psci";
+               };
+
+               a76_1: cpu@100 {
+                       compatible = "arm,cortex-a76";
+                       reg = <0x100>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779H0_PD_A1E0D0C1>;
+                       next-level-cache = <&L3_CA76>;
+                       enable-method = "psci";
+               };
+
+               a76_2: cpu@200 {
+                       compatible = "arm,cortex-a76";
+                       reg = <0x200>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779H0_PD_A1E0D0C2>;
+                       next-level-cache = <&L3_CA76>;
+                       enable-method = "psci";
+               };
+
+               a76_3: cpu@300 {
+                       compatible = "arm,cortex-a76";
+                       reg = <0x300>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779H0_PD_A1E0D0C3>;
+                       next-level-cache = <&L3_CA76>;
+                       enable-method = "psci";
                };
 
                L3_CA76: cache-controller {
@@ -53,6 +98,11 @@
                interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
 
+       psci {
+               compatible = "arm,psci-1.0", "arm,psci-0.2";
+               method = "smc";
+       };
+
        /* External SCIF clock - to be overridden by boards that provide it */
        scif_clk: scif-clk {
                compatible = "fixed-clock";