staging: iio: ad2s1210: Fix SPI reading
authorDragos Bogdan <dragos.bogdan@analog.com>
Wed, 29 Apr 2020 07:21:29 +0000 (10:21 +0300)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Sun, 3 May 2020 11:35:03 +0000 (12:35 +0100)
If the serial interface is used, the 8-bit address should be latched using
the rising edge of the WR/FSYNC signal.

This basically means that a CS change is required between the first byte
sent, and the second one.
This change splits the single-transfer transfer of 2 bytes into 2 transfers
with a single byte, and CS change in-between.

Note fixes tag is not accurate, but reflects a point beyond which there
are too many refactors to make backporting straight forward.

Fixes: b19e9ad5e2cb ("staging:iio:resolver:ad2s1210 general driver cleanup.")
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
drivers/staging/iio/resolver/ad2s1210.c

index 4b25a3a314edbc23af483024335e89251834e388..ed404355ea4c6f9978c941a953a014dd21f4f4fe 100644 (file)
@@ -130,17 +130,24 @@ static int ad2s1210_config_write(struct ad2s1210_state *st, u8 data)
 static int ad2s1210_config_read(struct ad2s1210_state *st,
                                unsigned char address)
 {
-       struct spi_transfer xfer = {
-               .len = 2,
-               .rx_buf = st->rx,
-               .tx_buf = st->tx,
+       struct spi_transfer xfers[] = {
+               {
+                       .len = 1,
+                       .rx_buf = &st->rx[0],
+                       .tx_buf = &st->tx[0],
+                       .cs_change = 1,
+               }, {
+                       .len = 1,
+                       .rx_buf = &st->rx[1],
+                       .tx_buf = &st->tx[1],
+               },
        };
        int ret = 0;
 
        ad2s1210_set_mode(MOD_CONFIG, st);
        st->tx[0] = address | AD2S1210_MSB_IS_HIGH;
        st->tx[1] = AD2S1210_REG_FAULT;
-       ret = spi_sync_transfer(st->sdev, &xfer, 1);
+       ret = spi_sync_transfer(st->sdev, xfers, 2);
        if (ret < 0)
                return ret;