riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsi

Add the 'cpus' label so that we can reference it in board dts files.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 9a2e9583af88d78d085584ab61a8ce211aa055c0..7de0732b8eabe4287395df8fb88fb510f0e66276 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -13,7 +13,7 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
-       cpus {
+       cpus: cpus {
                #address-cells = <1>;
                #size-cells = <0>;
 

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4a5708f7fcf7292f63fe975f3fd26cd7becc90d2..18047195c600bdca0f98ac64337d79e91ce202ab 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -15,7 +15,7 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
-       cpus {
+       cpus: cpus {
                #address-cells = <1>;
                #size-cells = <0>;