struct drm_display_info *display = &connector->display_info;
        struct drm_hdmi_info *hdmi = &display->hdmi;
        struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
+       int max_tmds_clock = 0;
+       u8 max_frl_rate = 0;
+       bool dsc_support = false;
 
        display->has_hdmi_infoframe = true;
 
         */
 
        if (hf_scds[5]) {
-               /* max clock is 5000 KHz times block value */
-               u32 max_tmds_clock = hf_scds[5] * 5000;
                struct drm_scdc *scdc = &hdmi->scdc;
 
+               /* max clock is 5000 KHz times block value */
+               max_tmds_clock = hf_scds[5] * 5000;
+
                if (max_tmds_clock > 340000) {
                        display->max_tmds_clock = max_tmds_clock;
-                       DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
-                               display->max_tmds_clock);
                }
 
                if (scdc->supported) {
        }
 
        if (hf_scds[7]) {
-               u8 max_frl_rate;
-
-               DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
                max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
                drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
                                     &hdmi->max_frl_rate_per_lane);
 
        drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
 
-       if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11])
+       if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
                drm_parse_dsc_info(hdmi_dsc, hf_scds);
+               dsc_support = true;
+       }
+
+       drm_dbg_kms(connector->dev,
+                   "HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
+                   max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
 }
 
 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,