coresight: etm4x: Do not save/restore Data trace control registers

ETM4x doesn't support Data trace on A class CPUs. As such do not access the
Data trace control registers during CPU idle. This could cause problems for
ETE. While at it, remove all references to the Data trace control registers.

Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
Reported-by: Yabin Cui <yabinc@google.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Tested-by: Yabin Cui <yabinc@google.com>
Link: https://lore.kernel.org/r/20240412142702.2882478-3-suzuki.poulose@arm.com

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index b9c6c544d7597f609249c59e7fd6344adbd443d4..a9765d45a0ee853c8eec655e6108f274962bedb1 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1739,9 +1739,6 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
        state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
        if (drvdata->nr_pe_cmp)
                state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
-       state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
-       state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
-       state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
 
        for (i = 0; i < drvdata->nrseqstate - 1; i++)
                state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
@@ -1872,9 +1869,6 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
        etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
        if (drvdata->nr_pe_cmp)
                etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
-       etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
-       etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
-       etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
 
        for (i = 0; i < drvdata->nrseqstate - 1; i++)
                etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 9ea678bc2e8e5503b014d26ce058ea3960731999..9e430f72bbd6fed8f6d2664d6ade0960d09857ef 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -43,9 +43,6 @@
 #define TRCVIIECTLR                    0x084
 #define TRCVISSCTLR                    0x088
 #define TRCVIPCSSCTLR                  0x08C
-#define TRCVDCTLR                      0x0A0
-#define TRCVDSACCTLR                   0x0A4
-#define TRCVDARCCTLR                   0x0A8
 /* Derived resources registers */
 #define TRCSEQEVRn(n)                  (0x100 + (n * 4)) /* n = 0-2 */
 #define TRCSEQRSTEVR                   0x118
@@ -90,9 +87,6 @@
 /* Address Comparator registers n = 0-15 */
 #define TRCACVRn(n)                    (0x400 + (n * 8))
 #define TRCACATRn(n)                   (0x480 + (n * 8))
-/* Data Value Comparator Value registers, n = 0-7 */
-#define TRCDVCVRn(n)                   (0x500 + (n * 16))
-#define TRCDVCMRn(n)                   (0x580 + (n * 16))
 /* ContextID/Virtual ContextID comparators, n = 0-7 */
 #define TRCCIDCVRn(n)                  (0x600 + (n * 8))
 #define TRCVMIDCVRn(n)                 (0x640 + (n * 8))
@@ -272,9 +266,6 @@
 /* List of registers accessible via System instructions */
 #define ETM4x_ONLY_SYSREG_LIST(op, val)                \
        CASE_##op((val), TRCPROCSELR)           \
-       CASE_##op((val), TRCVDCTLR)             \
-       CASE_##op((val), TRCVDSACCTLR)          \
-       CASE_##op((val), TRCVDARCCTLR)          \
        CASE_##op((val), TRCOSLAR)
 
 #define ETM_COMMON_SYSREG_LIST(op, val)                \
@@ -422,22 +413,6 @@
        CASE_##op((val), TRCACATRn(13))         \
        CASE_##op((val), TRCACATRn(14))         \
        CASE_##op((val), TRCACATRn(15))         \
-       CASE_##op((val), TRCDVCVRn(0))          \
-       CASE_##op((val), TRCDVCVRn(1))          \
-       CASE_##op((val), TRCDVCVRn(2))          \
-       CASE_##op((val), TRCDVCVRn(3))          \
-       CASE_##op((val), TRCDVCVRn(4))          \
-       CASE_##op((val), TRCDVCVRn(5))          \
-       CASE_##op((val), TRCDVCVRn(6))          \
-       CASE_##op((val), TRCDVCVRn(7))          \
-       CASE_##op((val), TRCDVCMRn(0))          \
-       CASE_##op((val), TRCDVCMRn(1))          \
-       CASE_##op((val), TRCDVCMRn(2))          \
-       CASE_##op((val), TRCDVCMRn(3))          \
-       CASE_##op((val), TRCDVCMRn(4))          \
-       CASE_##op((val), TRCDVCMRn(5))          \
-       CASE_##op((val), TRCDVCMRn(6))          \
-       CASE_##op((val), TRCDVCMRn(7))          \
        CASE_##op((val), TRCCIDCVRn(0))         \
        CASE_##op((val), TRCCIDCVRn(1))         \
        CASE_##op((val), TRCCIDCVRn(2))         \
@@ -907,9 +882,6 @@ struct etmv4_save_state {
        u32     trcviiectlr;
        u32     trcvissctlr;
        u32     trcvipcssctlr;
-       u32     trcvdctlr;
-       u32     trcvdsacctlr;
-       u32     trcvdarcctlr;
 
        u32     trcseqevr[ETM_MAX_SEQ_STATES];
        u32     trcseqrstevr;