drm/amdgpu: Add register read/write debugfs support for AID's

SMN address is larger than 32 bits for registers on different AID's
Updating existing interface to support access to such registers.

Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 2cebf2145d9a6e726357a89924963cab461d740e..e485dd3357c63fd225b3fb7e3847675749f018da 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -540,7 +540,11 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
        while (size) {
                uint32_t value;
 
-               value = RREG32_PCIE(*pos);
+               if (upper_32_bits(*pos))
+                       value = RREG32_PCIE_EXT(*pos);
+               else
+                       value = RREG32_PCIE(*pos);
+
                r = put_user(value, (uint32_t *)buf);
                if (r)
                        goto out;
@@ -600,7 +604,10 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user
                if (r)
                        goto out;
 
-               WREG32_PCIE(*pos, value);
+               if (upper_32_bits(*pos))
+                       WREG32_PCIE_EXT(*pos, value);
+               else
+                       WREG32_PCIE(*pos, value);
 
                result += 4;
                buf += 4;