KVM: selftests: get-reg-list: add Permission Indirection registers

Add new system registers:
  - ID_AA64MMFR3_EL1
  - TCR2_EL1
  - PIRE0_EL1
  - PIR_EL1

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: Mark Brown <broonie@kernel.org>
Cc: Shuah Khan <shuah@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20230606145859.697944-21-joey.gouly@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
index 3ab236ceb6fc9f01a352888b17b96229abb1e83c..4f10055af2aa2e25bfb9e5f376be6cf7e9060a4f 100644 (file)
--- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c
+++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
@@ -56,6 +56,24 @@ struct feature_id_reg {
 };
 
 static struct feature_id_reg feat_id_regs[] = {
+       {
+               ARM64_SYS_REG(3, 0, 2, 0, 3),   /* TCR2_EL1 */
+               ARM64_SYS_REG(3, 0, 0, 7, 3),   /* ID_AA64MMFR3_EL1 */
+               0,
+               1
+       },
+       {
+               ARM64_SYS_REG(3, 0, 10, 2, 2),  /* PIRE0_EL1 */
+               ARM64_SYS_REG(3, 0, 0, 7, 3),   /* ID_AA64MMFR3_EL1 */
+               4,
+               1
+       },
+       {
+               ARM64_SYS_REG(3, 0, 10, 2, 3),  /* PIR_EL1 */
+               ARM64_SYS_REG(3, 0, 0, 7, 3),   /* ID_AA64MMFR3_EL1 */
+               4,
+               1
+       }
 };
 
 struct vcpu_config {
@@ -873,12 +891,15 @@ static __u64 base_regs[] = {
        ARM64_SYS_REG(3, 0, 2, 0, 0),   /* TTBR0_EL1 */
        ARM64_SYS_REG(3, 0, 2, 0, 1),   /* TTBR1_EL1 */
        ARM64_SYS_REG(3, 0, 2, 0, 2),   /* TCR_EL1 */
+       ARM64_SYS_REG(3, 0, 2, 0, 3),   /* TCR2_EL1 */
        ARM64_SYS_REG(3, 0, 5, 1, 0),   /* AFSR0_EL1 */
        ARM64_SYS_REG(3, 0, 5, 1, 1),   /* AFSR1_EL1 */
        ARM64_SYS_REG(3, 0, 5, 2, 0),   /* ESR_EL1 */
        ARM64_SYS_REG(3, 0, 6, 0, 0),   /* FAR_EL1 */
        ARM64_SYS_REG(3, 0, 7, 4, 0),   /* PAR_EL1 */
        ARM64_SYS_REG(3, 0, 10, 2, 0),  /* MAIR_EL1 */
+       ARM64_SYS_REG(3, 0, 10, 2, 2),  /* PIRE0_EL1 */
+       ARM64_SYS_REG(3, 0, 10, 2, 3),  /* PIR_EL1 */
        ARM64_SYS_REG(3, 0, 10, 3, 0),  /* AMAIR_EL1 */
        ARM64_SYS_REG(3, 0, 12, 0, 0),  /* VBAR_EL1 */
        ARM64_SYS_REG(3, 0, 12, 1, 1),  /* DISR_EL1 */