* @periodic: Set if this is a periodic ep, such as Interrupt
  * @isochronous: Set if this is a isochronous ep
  * @send_zlp: Set if we need to send a zero-length packet.
+ * @desc_list_dma: The DMA address of descriptor chain currently in use.
+ * @desc_list: Pointer to descriptor DMA chain head currently in use.
+ * @desc_count: Count of entries within the DMA descriptor chain of EP.
  * @total_data: The total number of data bytes done.
  * @fifo_size: The size of the FIFO (for periodic IN endpoints)
  * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
 #define TARGET_FRAME_INITIAL   0xFFFFFFFF
        bool                    frame_overrun;
 
+       dma_addr_t              desc_list_dma;
+       struct dwc2_dma_desc    *desc_list;
+       u8                      desc_count;
+
        char                    name[10];
 };
 
 
        dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
                __func__, epctrl, epctrl_reg);
 
+       /* Allocate DMA descriptor chain for non-ctrl endpoints */
+       if (using_desc_dma(hsotg)) {
+               hs_ep->desc_list = dma_alloc_coherent(hsotg->dev,
+                       MAX_DMA_DESC_NUM_GENERIC *
+                       sizeof(struct dwc2_dma_desc),
+                       &hs_ep->desc_list_dma, GFP_KERNEL);
+               if (!hs_ep->desc_list) {
+                       ret = -ENOMEM;
+                       goto error2;
+               }
+       }
+
        spin_lock_irqsave(&hsotg->lock, flags);
 
        epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
                        dev_err(hsotg->dev,
                                "%s: No suitable fifo found\n", __func__);
                        ret = -ENOMEM;
-                       goto error;
+                       goto error1;
                }
                hsotg->fifo_map |= 1 << fifo_index;
                epctrl |= DXEPCTL_TXFNUM(fifo_index);
        /* enable the endpoint interrupt */
        dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
 
-error:
+error1:
        spin_unlock_irqrestore(&hsotg->lock, flags);
+
+error2:
+       if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
+               dma_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
+                       sizeof(struct dwc2_dma_desc),
+                       hs_ep->desc_list, hs_ep->desc_list_dma);
+               hs_ep->desc_list = NULL;
+       }
+
        return ret;
 }
 
                return -EINVAL;
        }
 
+       /* Remove DMA memory allocated for non-control Endpoints */
+       if (using_desc_dma(hsotg)) {
+               dma_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
+                                 sizeof(struct dwc2_dma_desc),
+                                 hs_ep->desc_list, hs_ep->desc_list_dma);
+               hs_ep->desc_list = NULL;
+       }
+
        epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
 
        spin_lock_irqsave(&hsotg->lock, flags);