phy: qcom-qmp: pcs: Add v6.20 register offsets

The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new PCS offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-4-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
new file mode 100644 (file)
index 0000000..9c3f1e4
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V6_20_H_
+#define QCOM_PHY_QMP_PCS_V6_20_H_
+
+/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */
+#define QPHY_V6_20_PCS_G3S2_PRE_GAIN                   0x178
+#define QPHY_V6_20_PCS_RX_SIGDET_LVL                   0x190
+#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL            0x1b8
+#define QPHY_V6_20_PCS_TX_RX_CONFIG1                   0x1dc
+#define QPHY_V6_20_PCS_TX_RX_CONFIG2                   0x1e0
+#define QPHY_V6_20_PCS_EQ_CONFIG4                      0x1f8
+#define QPHY_V6_20_PCS_EQ_CONFIG5                      0x1fc
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 80e3b5c860b6cf65e3d8a124f534757b248ca799..760de4c76e5bbfbf9d8b46e7186688c2788a7c4c 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -40,6 +40,8 @@
 
 #include "phy-qcom-qmp-pcs-v6.h"
 
+#include "phy-qcom-qmp-pcs-v6_20.h"
+
 /* Only for QMP V3 & V4 PHY - DP COM registers */
 #define QPHY_V3_DP_COM_PHY_MODE_CTRL                   0x00
 #define QPHY_V3_DP_COM_SW_RESET                                0x04